The advent of mosaic focal planes, with their accompanying complexity, demands a clear delineation and a wide perspective of architectural levels for the optimum design and integration of focal planes. This overview describes the important characteristics of the various architectural levels, pinpoints the main constraints on focal plane architecture and highlights the major issues and trends in focal plane technology.

A new IR detector/CCD multiplexer interfacing scheme is presented which utilizes an array of photocapacitive detectors coupled directly to a CCD multiplexer. The Direct Capacitive Coupling (DCC) input is potentially superior to conventional diode coupling schemes, i.e., direct injection or gate modulation, in terms of noise, anti-blooming characteristics and effective utilization of chip area. The DCC input is compatible with various background suppression techniques which have been developed for the diode coupling schemes. A detailed analysis of the performance of a DCC input is presented in this paper.

Recent advances in the field of infrared focal planes provide the detector array technology needed to manufacture monolithic and hybrid detector arrays containing large numbers of detectors with buffer amplifiers and multiplexing on a single LSI chip. Infrared focal planes of the future will require the integration of these detector/multiplexer arrays together with support electronics into a manufacturable, testable, reliable, and maintainable IFPA. The IFPA must efficiently interface with cryogenic systems, optics, mechanical structures, and signal processing electronics. Hughes Aircraft Company has conducted a study to determine what technologies are needed to support the assembly of large infrared focal planes. This paper discusses the results of this IFPA study and the progress being made in developing such technologies. Cyrogenic chip carriers, high-density electrical interconnects, multilayered electrical interconnects, and high-density cables are discussed in terms of an architectural approach as it relates to the manufacture, test, and assembly of IFPAs. An integrated focal plane array design is presented to exemplify the validity of this IFPA design approach. The example IFPA design includes, identification of critical test methodologies, assembly techniques, and electrical interconnect requirements that will challenge the state of the art of focal plane assembly and manufacture. Large IFPAs of the next decade will pose new challenges in focal plane architecture, cryogenic high-density cables, and electrical interconnects as well as in cryogenic thermal design and test. This paper presents a modular IFPA design approach that provides solutions to these challenges.

The XCED (extrinsic charge-extraction device) is a unique focal-plane array structure designed for staring infrared-imaging applications. Extrinsic-silicon detectors, MOS integrating storage capacitors, and unique accumulation mode multiplexing devices are combined in a two-dimensional array within a single monolithic chip. Zinc-doped silicon has been studied and utilized to fabricate detectors sensitive in the 2 to 4 Ilm spectral band with BLIP operating temperatures above 110°K. The potentially severe problems for staring arrays of element-to-element nonuniformities and detector storage saturation have been solved. Preliminary results and thermal imagery are shown for a 16 x 16 element array.

Sophisticated infrared imaging systems require complex focal plane device structures to perform the basic functions of (1) detection, (2) time-delay-and-integration (TDI), (3) multiplexing, and possibly (4) scanning in large array formats with minimal on-focal-plane power dissipation. Monolithic HgCdTe charge transfer device structures are promising candidates for many focal plane requirements. Charge coupled devices (CCDs) are the natural structure for scanning system focal pl.nes which utili:e TN. Charge injection devices (CID's) are directly applicable to staring system focal plane requirements. This paper discusses the applicability and design considerations of various devices which have been developed using this technology.

On Chip CCD Signal Processing Circuits are presented which enhance Focal Plane performance in scanned imaging systems. A Charge Input Mode Programmable Signal CHIMPS Compressor increases dynamic range by providing programmable signal amplitude compression at the detector. Compression breakpoint and ratio are determined by clocking waveforms. A CCD Multiplier provides Automatic Responsivity Control ARC to reduce TDI column to column responsivity non-uniformities. A GAMMA - APERTURE circuit provides two functions: (1) high frequency boost to compensate for losses due to scanning of detector apertures, and (2) a scene processing gamma function which attenuates high level, low frequency signals. This circuit provides increased useable dynamic range when observing scene detail contained in large scene areas which have large differences in amplitude.

The Digicon has been chosen by NASA as the detector for two of the focal plane instruments on the Space Telescope. Both detectors are 512 channel, parallel output devices and feature photon-counting capability. Recently, tubes for this application have been fabri-cated and tested at Electronic Vision Company. Using a unique computer-assisted test facility, these tubes have been characterized with respect to diode array performance, photocathode response (1100-9000 Å), and imaging capability. In this paper, data are pre-sented on diode dark current and capacitance distributions, pulse height resolution, photocathode quantum efficiency, uniformity and blemishes, dark count rate, distortion, resolution, and crosstalk. Results indicate that the Space Telescope Digicon is capable of extremely low-noise performance in the pulse counting mode.

It is now widely accepted that the next generation of infrared focal planes will be two-dimensional mosaics of infrared sensing detectors interfaced with charge transfer cells. One form in which these devices is presently being implemented is with hybrid structures using silicon CCDs for charge transfer, and infrared detectors for photon sensing, both being optimized for the desired application. The basic design of the IR/CCD is controlled by the interface requirements, both mechanical and electrical, wherein the response to photon flux is transferred, physically and electrically, from the detector through the input network to end up as charge in a CCD well. The charge is then laterally transferred off the focal plane in multiplex form. Proper design results in negligible loss in signal-to-noise ratio compared to discrete devices. This paper discusses the architecture and the design of the hybrid IR/CCD from the interface point of view, including planar and bump mechanical configurations, and electrical coupling networks. A summary of state of the art will be presented for detectors, CCDs, and IR/CCD focal planes.

Both visible and infrared focal plane assemblies have common architectural driving parameters which guide their design approaches. The key drivers for advanced focal plane assemblies (FPA) are: the detector type and performance required; the number of detector chips; the packaging density; and the geometry. The impact of these drivers is seen to determine the engineering compromises necessary to establish FPA design approach. Several new designs are discussed which show a range of applications from single detector assemblies to monolithic detector chips with on-chip signal processing. The main objective of many advanced designs is to integrate the focal plane components in order to reduce power and re-duce the number of interconnections. The next stage of integration may come with VLSI device developments.

CCD shift registers have been investigated in 4.4 pm HgCdTe for time delay and integrate (TDI) enhancement of responsivity and signal to noise ratio and for multiplexing a number of TDI shift registers. CCD linear arrays and area arrays have been operated from 77K to 140K cooling and from 50 kHz to above 1 MHz. Charge transfer efficiency (CTE) has been measured to 0.9999 on a 32 stage four phase p channel device. Infrared sensitivity measure-ments show, D* values above 10¹² cmHz^1/2/W for full TDI enhancement of32. TDI has been demonstrated utilizing focused laser illumination scanned synchronously with the clocked charge. Sensitivity and noise analyses have been made to show limits of detection for multiplexed arrays.

Advances in epitaxial hgCdTe/CdTe material technology such as high crystalline quality and surface morphology have motivated the study of MIS devices and the current development of CCDs in these heterostructures. Results of MIS device studies in n-and p-type HgCdTe/CdTe structures are presented. Annealing in Hg atmosphere was used to obtain n 10¹⁴ cm^-3 and p 5 x 10¹⁵ cm³. A native oxide passivation used in conjunction with ZnS has yielded high-integrity MIS interfaces for n-type epilayers. For p-type HgCdTe/CdTe, n⁺/p junction technology and ZnS passivation have been used to demonstrate enhancement-mode MISFETs. These results indicate the feasibility of MISCCDs in HgCdTe/CdTe structures, with particularly attractive features in n-channel (p-type) devices.

We describe the performance of two types of monolithic silicon IRCCD focal planes with platinum-silicide Schottky-barrier detectors. They are a 256 element line array and a 25X50 element area array. Both focal planes are entirely monolithic with Schottky photodiodes, buried channel CCD shift registers and output amplifiers all processed as a standard IC chip. These devices are sensitive in the 1.2 to 4.9 μm range but they are normally optically filtered to the 3.4 to 4.2 μm range. Their operating temperature is 77°K. A typical value of quantum-Lfficiency coefficient (C1) of the platinum-silicide photodiode was 5 to 77/eV for a 600 .R Pt deposition; however, recently focal planes have been fabricated with thin Pt deposition and C1 values have increased to > 257/eV. This increased quantum yield has resulted in devices with a noise equivalent irradiance (NEIL) of better than 0.1 µw/cm2.

A 6144 X 64 pixel focal plane assembly has been constructed incorporating six 1024 X 64 Time Delay and Integration Charge-Coupled Devices (TDI CCDs) in a beam-sharer configuration. The beam-sharer approaches 100 percent efficiency over the format, compared to a maximum 50 percent efficiency for a conventional beam-splitter configuration. The TDI CCDs have 20 X 20 micrometer pixels. The focal plane assembly is constructed so that the pixels are contiguous at the optical "butt" between chips to within 2 micrometers and straight within a 6 micrometer error band over the entire six chip length. These dimensional accuracies were achieved using a precision alignment apparatus developed for this purpose. In a way similar to a comparator microscope, its optical system provides simultaneous overlapping fields of view; one incorporates fixed reference lines while the other contains a view of the CCD chips. A mechanical micro-manipulator is used to provide precise control of chip motion in three degrees of freedom (x, y, 0) for each of the two CCD mounting planes. The modular focal plane assembly technique makes practical the fabrication of large-format, gapless configurations of high optical efficiency. Both the assembly technique and methodology of subsequent repair (replacement of chips after some period of service, should that ever be required) are described in detail.

In this paper we describe the considerations necessary 1Dr the optimization of CCD area array sensors for x-rays in the 0.5-15KeV energy range. It is shown that a backside illuminated, unthinned (-10 mil thick) deep depletion mode CCD fabricated on a high resis-tivity substrate (-15 KΩ-cm) is best for imaging with this x-ray range. Preliminary data demonsttating the functionality of such an area array is presented. Line array test structures fabricated along with the area array indicate that transfer efficiency for this CCD was better than 0.9999 when operated at 80^oK. A slit imaged in the backside illuminated mode gave image with a FWHM approximately 60μm. The full well capacity of a 60μm x 20μm pixel was approximately 5 x 10 charges. X-ray sensitivity was demonstrated using MnTc photons ( 5.9 KeV). Large leakage currents were encountered due to the deep depletion. However,one sigma uncertainty in signal caused by generation was ^-77 charges at 80^oK.

The fabrication of a monolithic indium-antimonide 32 x 32 CID array applicable for staring infrared imaging sensors is presented with preliminary characterization results. The basic MIS technology utilizes low-temperature CVD to deposit insulating layers of nitrogen-doped Si0₂ on bulk indium-antimonide substrates. A two-level insulator/two-level metal structure results in a simple four-mask process flow for the CID array. Completed arrays demonstrate acceptable dark currents that result in 20 ms storage times at 77K and are completely photocurrent dominated for typical tactical background photon flux densities in the 10¹⁵ to 10¹⁶ photons/cm²s range. Charge transfer experiments indicate acceptable transfer efficiencies for CID operation. Plans to demonstrate thermal imagery are presented.

Recent progress in infrared focal plane array technology has been impressive and has aroused strong systems interest. This paper will summarize the present general state of focal plane development and will identify some of the major technology issues still to be resolved. Some of the implications of the properties of focal plane arrays for systems design will be discussed.

The potential utility of integrated focal planes to the Army's second-generation IR imagers is well established. Over the past four years, the Night Vision and Electro-Optics Laboratory has initiated several hardware-development programs designed to integrate large detector arrays with CCD signal processing in one structure. These programs focused on general architecture design and fabrication feasibility, i.e., the electrical/mechanical interface between detector and CCD for various IR backgrounds and scan techniques. Although not all the architecture problems are completely solved, the attention is now turning toward the more practical aspects of implementing focal plane technology, such as economical testing and device reliability. Test procedures, relatively trivial for low-density linear arrays, are neither simple nor standard for the high-density detector/CCD mosaics. The reliability of the sensor will depend on both the inherent quality and the stability of the detector/CCD structure and the integrity of the dewar assembly. New materials and processes, possible metallurgical incompatibility, and uncertain limits on anneal and bakeout temperatures are all factors in estimating the sensor's operating life. This paper reviews some of the unresolved technical issues concerning advanced focal planes and addresses the Army's concern with testing and predicting reliability of the second-generation sensor.

The major requirements in focal plane signal processing for scanned CID's are the low noise detection of signal charge, the enhancement of signal to noise ratio, the rejection of background signal and the low noise multiplexing of data onto a few signal lines. For implementation on the focal plane, these functions must be designed to operate at cryogenic temperatures, where bipolar and JFET technologies are inappropriate for reasons of low gain or high noise. It is proposed that a combination of linear MOS and Charge Coupled Device technology is the most appropriate for implementing scanned CID systems and in this paper the design and evaluation of these circuit functions are discussed. The implementation of an optimum design for a low noise MOS preamplifier is first considered followed by a discussion of the design aspects of a time delay and integrate device. The novel implementation of a high pass filter in conjunction with a low noise multiplexer completes the focal plane design. Experimental results obtained from a number of fabricated devices will be presented to illustrate the relative maturity of the design approach.

Nonscanned staring thermal imagers for portable applications have many advantages if the fixed-pattern noise caused by elemental non-uniformities can be compensated in a low-power configuration operating in real time. A novel approach to this problem has been developed using a multiple-loop fold-back technique. This technique corrects for both gain and level non-uniformities in real time and allows for either updating the stored correction data or for a permanent compensation approach. The total power consumption for this technique is less than 50 microwatts in a volume of less than 0.001 cubic inches per picture element. The modular approach makes this compensation technique applicable to arrays of all sizes in any application of staring infrared imagers.

The invention of the charged coupled device (CCD) almost ten years ago and the utility of the charge transfer device (C'I'D) in general has made development of mosaic focal planes possible. The nature of the metal-oxide semiconductor (MOS) manufacturing processes utilized in most CTlls posed special requirements for material, process control, and device evaluation which have been and still are, the object of intensive technology development programs in the past several years. Achieving the long-standing goals of high-volume, low-cost production potential of the technology for mosaic focal planes is still in the future. The degree of achievement of these goals will depend a great deal upon adoption of some standardization of device architecture, operating conditions, test parameters, and evaluations techniques. Production of these devices will require capital investments for dedicated specialized facilities necessary to achieve volume production.

Several staring IR focal planes have been measured under reduced background conditions. A number of experimental problems have been encountered. These problems will be presented and discussed.

Nuclear and space radiation can produce a number of undesirable effects in infrared detectors. Steady-state ionizing particle fluxes, such as electron, proton, or gamma fluxes, produce a series of pulses in both intrinsic and extrinsic detectors. Many of these pulses have amplitudes large enough to result in their detection as false signals by the sensor. Alternatively, the combined effect of such pulses is to increase the rms noise level and the leakage current in the detector. Steady-state ionizing fluxes also cause an increase or a decrease in the optical response in extrinsic silicon detectors as a result of the trapping of the ionization-generated carriers on the optically active sites. Displacement damage, caused by electron, proton, or neutron fluences, gives rise to centers that decrease the optical responsivity. In extrinsic detectors, this decrease is the result of the radiation-induced defects compensating the optically active sites. Total-dose deposition has its largest effect in insulators and at semiconductor-insulator interfaces. This is particularly trouble-some in detector arrays where interaction between previously isolated elements can result. Total-dose deposi-tion can also affect the characteristics (decreased zero-bias resistance and increased reverse leakage current) of photovoltaic detectors. The purpose of this paper is to present an overview of the effects that radiation can produce in infrared detectors.

Flatband voltage shifts on ther order of -2 volts/10⁴ rad (Si) are observed for all MOS devices with 1000 R thick oxides irradiated at temperatures below 100°K. For example, the radiation hardness of "process optimized" oxides, which are radiation hard at room temperature with threshold shifts of -1V/10⁶ rad (Si) for 1000 Å oxides, is degraded by two orders of magnitude when irradiated below 100°K. Flatband voltage shifts as small as0-1 volt per 10⁶ rad (Si) have been measured on thin oxide MNOS capacitors irradiated at 80 K. The threshold shift in a p-buried channel CCD linear shift register, fabricated with an oxide/ nitride dual gate insulator and double-level polysilicon gates and irradiated with the device operating, was -1 volt after 10° rad (Si) dose at 80°K. The CCDs were operational using the preirradiation bias conditions after 10° rad (Si) at 80°K, and the CCD transfer efficiency was essentially unchanged at 0.9999.

The demands of many mission requirements have greatly increased the need for a common approach to IR focal planes that is flexible enough to meet these demands without major changes of technology. Hybrid HgCdTe focal planes represent a potential solution to these mission requirements. Recent developments in HgCdTe liquid phase epitaxial technology have produced device quality epitaxial layers grown on transparent CdTe substrates with cut-off wavelength uniformity of < ± 0.1 μm at 11 μm and < ± 0.01 μm at 4.8 μm. Devices fabricated in these layers by ion implantation show broad band spectral response with high quantum efficiency (up to 79% external without Ar coating). RoA values appear to be limited by bulk properties at temperatures at least as low as 80K for all wavelengths investigated. Both MWIR and LWIR devices have exhibited limited diffusion volume enhancement of performance at temperatures where diffusion mechanisms dominate reverse bias current characteris-tics. Hybrid structures have been fabricated and evaluated; the preliminary results indicate the suitability of these mosaics for hybrid focal plane applications.

Second generation infrared imaging systems require high density focal plane arrays for both staring and scanned applications. To meet these needs, a focal plane structure using HgCdTe photodiodes for detectors and Si CCDs for signal processing has been developed. Although conventional ion implanted hybrid arrays have successfully been interfaced to CCD multiplexers, hybrid arrays fabricated on LPE layers offer some inherent advantages with respect to performance, processing and yields. It has been determined that hetero-structure diodes fabricated by a Hg infinite melt LPE technique give superior performance relative to conventional ion implanted devices. The devices consist of n-type LPE layers grown on p-type substrates. The layers are n-type as grown and no annealing of the grown layer is required. The deVices exhibit high R_oA products and good compositional uniformity. Data will be presented on devices fabricated for both 8- to 12-µm and 3- to 5-µm applications.

Current research on infrared hybrid focal planes is directed toward devices in which detection occurs in a p-n junction formed in an intrinsic narrow energy bandgap semiconductor, and signal processing is accomplished in a Si CCD multiplexer which is electrically interfaced to the detector array. A hybrid array such as this, where the detector format is a 32 x 32 matrix, has been fabricated. The active material is backside-illuminated InAsSb which has been planar processed and fully passivated. The cutoff wavelength is 4.0 μm at the operating temperature of 77K. The CCD is four phase with a two level polysilicon gate structure. The signal input is via direct injection with an option for dc suppression. Operation of the focal plane in a staring mode that uses dc suppression is discussed. Data derived from the video output is presented; this includes responsivity and detectivity. Off focal plane non-uniformity compensation is also discussed. Displays of thermal images utilizing processed data from the hybrid focal plane array will be shown.

Multichannel high speed arrays incorporating amplifiers and signal processors within a single package (flat pack or modular side wall) are available from MERET. Ranging from quadrant modules to 2 x 16 matrix formats, these systems are designed for high speed (less than 10 ns rise/fall time), large active area per element (80 mils on a side typically for the 16-element arrays), and fine resolution (less than 5 mil separation between elements). Responsivity of better than 4 mV/ μW consistent with NEP on the order of 5 nW is easily achievable on a low cost system.

A pyroelectric detector/Si CCD hybrid focal plane operates at room temperature, and may prove useful in applications where the sensor performance requirement is moderate but low cost is essential. Flip-chip, bump mounted LiTa0₃/CCD modules are under development at Honeywell (see Figure 1). A one dimensional thermal model of the pyroelectric detector response has been developed. The detector element is modeled as a continuous one dimensional thermal transmission line, consisting of three thermally conductive layers corresponding to the pyroelectric, bump and Si CCD substrate, with the far surface of the substrate layer affixed to an ideal heat sink. The thermal conduction equations were solved exactly within the layers, and from the solutions obtained for the appropriate boundary conditions, the thermal and voltage responsivities were derived as functions of frequency. The responsivities exhibit flat response at low frequencies and a 1/s roll off at high frequencies. The flat portion is dependent only on the thermal conductances of the three layers, while the 1/s portion is dependent only on the heat capacity of the pyroelectric layer. The analysis has been applied to the real pyroelectric devices.

Pyroelectric detectors have the advantage of being inherently accoupled to the target scene and they are therefore ideally suited for use in high-background and/or long-wavelength thermal imaging systems. This paper presents the results of a study to determine the feasibility and to predict the performance of focal planes employing very thin pyroelectric detector arrays together with solid-state readout circuitry. Detectivities within a factor of two of the radiation-limited performance have been achieved by wire bond connecting pyroelectric detectors to a Hughes CCD with a modulating gate input. It is shown that the voltage responsivity is symmetric with respect to the thermal and electrical time con-stants; the traditional role of these time constants (Tpc < Til) can be reversed to that Tw. becomes greater than Tth. The lumped parameter analysis creaks down for very thin detectors when the thermal time constant must be severely adjusted and for detector arrays in the absence of adequate thermal isolation between elements; in this case, thermal spreading must be accounted for. A more extensive treatment utilizing a thermal diffusion analysis allows such cases to be considered.