Overlay (OVL) metrology targets are typically distributed across the scribe lines of the grid on a semiconductor wafer. However, OVL target placement across peripheral scribe lines or intra-field scribe lines cannot always describe the OVL measurement of interest, especially when the OVL distribution is of high order. The OVL measurement of interest lies within the device, in the center of the field or the center of die. This work aims to emphasize the need for intra-field metrology simulations to quantify the impact of scribe line target usage in the presence of a high order intra-field OVL map. The analysis will cover the impact of scanner aberration, target location, sampling and model error on OVL results. To complete the picture, a wafer map will be simulated with high order OVL error distributions both outer-field and intra-field. We will present the tradeoff between high sampling, target location and accuracy.
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