32-nm SOC printing with double patterning, regular design, and 1.2 NA immersion scanner

Yorick Trouiller; Vincent Farys; Amandine Borjon; Jérôme Belledent; Christophe Couderc; Frank Sundermann; Jean-Christophe Urbani; Yves Rody; Christian Gardin; Jonathan Planchot; Will Conley; Pierre-Jerome Goirand; Scott Warrick; Frédéric Robert; Gurwan Kerrien; Florent Vautrin; Bill Wilkinson; Mazen Saied; Emic Yesilada; Patrick Montgomery; Laurent Le Cam; Catherine Martinelli

doi:10.1117/12.714116

27 March 2007 32-nm SOC printing with double patterning, regular design, and 1.2 NA immersion scanner

Yorick Trouiller, Vincent Farys, Amandine Borjon, Jérôme Belledent, Christophe Couderc, Frank Sundermann, Jean-Christophe Urbani, Yves Rody, Christian Gardin, Jonathan Planchot, Will Conley, Pierre-Jerome Goirand, Scott Warrick, Frédéric Robert, Gurwan Kerrien, Florent Vautrin, Bill Wilkinson, Mazen Saied, Emic Yesilada, Patrick Montgomery, Laurent Le Cam, Catherine Martinelli

Author Affiliations +

Proceedings Volume 6520, Optical Microlithography XX; 65201D (2007) https://doi.org/10.1117/12.714116
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from: -Static RAM with very aggressive design rules specially at active, poly and contact -transistor variability control at the chip level -random layouts The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm : -dipole with polarization and regular layout for active level -dipole with polarization, regular layout and double patterning to cut the line-end for poly level. These choices have been made based on the printing performances of a 0.17&mgr;m² SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.

Citation Download Citation

Yorick Trouiller, Vincent Farys, Amandine Borjon, Jérôme Belledent, Christophe Couderc, Frank Sundermann, Jean-Christophe Urbani, Yves Rody, Christian Gardin, Jonathan Planchot, Will Conley, Pierre-Jerome Goirand, Scott Warrick, Frédéric Robert, Gurwan Kerrien, Florent Vautrin, Bill Wilkinson, Mazen Saied, Emic Yesilada, Patrick Montgomery, Laurent Le Cam, and Catherine Martinelli "32-nm SOC printing with double patterning, regular design, and 1.2 NA immersion scanner", Proc. SPIE 6520, Optical Microlithography XX, 65201D (27 March 2007); https://doi.org/10.1117/12.714116

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