Digital tapped delay lines for HWIL testing of matched filter radar receivers

Richard F. Olson; William J. Braselton; Richard D. Mohlere

doi:10.1117/12.819136

22 April 2009 Digital tapped delay lines for HWIL testing of matched filter radar receivers

Richard F. Olson, William J. Braselton, Richard D. Mohlere

Proceedings Volume 7301, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XIV; 73010D (2009) https://doi.org/10.1117/12.819136
Event: SPIE Defense, Security, and Sensing, 2009, Orlando, Florida, United States

Abstract

Matched filter processing for pulse compression of phase coded waveforms is a classic method for increasing radar range measurement resolution. A generic approach for simulating high resolution range extended radar scenes in a Hardware in the Loop (HWIL) test environment is to pass the phase coded radar transmit pulse through an RF tapped delay line comprised of individually amplitude- and phase-weighted output taps. In the generic approach, the taps are closely spaced relative to time intervals equivalent to the range resolution of the compressed radar pulse. For a range-extended high resolution clutter scene, the increased number of these taps can make an analog implementation of an RF tapped delay system impractical. Engineers at the U.S. Army Aviation and Missile Research, Development and Engineering Center (AMRDEC) have addressed this problem by transferring RF tapped delay line signal operations to the digital domain. New digital tapped delay line (DTDL) systems have been designed and demonstrated which are physically compact compared to analog RF TDLs, leverage low cost FPGA and data converter technology, and may be readily expanded using open slots in a VME card cage. In initial HWIL applications, the new DTDLs have been shown to produce better dynamic range in pulse compressed range profiles than their analog TDL predecessors. This paper describes the signal requirements and system architecture for digital tapped delay lines. Implementation, performance, and HWIL simulation integration issues for AMRDEC's first generation DTDLs are addressed. The paper concludes with future requirements and plans for ongoing DTDL technology development at AMRDEC.

Citation Download Citation

Richard F. Olson, William J. Braselton, and Richard D. Mohlere "Digital tapped delay lines for HWIL testing of matched filter radar receivers", Proc. SPIE 7301, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XIV, 73010D (22 April 2009); https://doi.org/10.1117/12.819136

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
9 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Digital filtering

Radar

Analog electronics

Field programmable gate arrays

Computing systems

Filtering (signal processing)

Data conversion

Show All Keywords

Keywords/Phrases

Search In:

Publication Years