Using a mask rule checker as an electrical rule checker

Philippe Morey-Chaisemartin; Eric Beisser

doi:10.1117/12.2028657

28 June 2013 Using a mask rule checker as an electrical rule checker

Philippe Morey-Chaisemartin, Eric Beisser

Proceedings Volume 8701, Photomask and Next-Generation Lithography Mask Technology XX; 87010D (2013) https://doi.org/10.1117/12.2028657
Event: Photomask and NGL Mask Technology XX, 2013, Yokohama, Japan

Abstract

Design complexity sometimes grows faster than EDA tools performances, and some innovation should be made on the design flow to guarantee the best possible validation in a reasonable time. This was the challenge we were facing for the final layout validation of a 3 billions transistors, multi cores chip designed for a 28nm process. The design backend validation requires multiple tools: the LVS to check connectivity, the DRC to check layout rules and the ERC to check any risk of power drop among the whole chip. While the 2 first tools are able to deal with huge designs by using hierarchical approaches, Electrical Rule Checking is much more complicated as the power routing is generally made flat at the top level of the chip. The classical ERC tools were not able to validate the power distribution at top level. The power distribution was made through a power grid using two metal layers and arrays of vias to connect each block at deeper metal layers. The chip is made of 256 processors and has a quite regular structure so that each module has it own power grid with the same pitch and every thing should be butting or properly connected at top level. It has then been decided to use a very efficient tool dedicated to geometrical verification of flat designs (typically a Mask Rule Checker) to check any interruption on power lines or missing vias in arrays. This paper will describe how this validation was performed as well as the performances obtained on a 28nm, 3 billions transistors design.

Citation Download Citation

Philippe Morey-Chaisemartin and Eric Beisser "Using a mask rule checker as an electrical rule checker", Proc. SPIE 8701, Photomask and Next-Generation Lithography Mask Technology XX, 87010D (28 June 2013); https://doi.org/10.1117/12.2028657

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
7 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Metals

Computer aided design

Transistors

Resistors

Databases

Power supplies

Switches

Show All Keywords

Keywords/Phrases

Search In:

Publication Years