Layout finishing of a 28nm, 3 billions transistors, multi-core processor

Philippe Morey-Chaisemartin; Eric Beisser

doi:10.1117/12.2028314

28 June 2013 Layout finishing of a 28nm, 3 billions transistors, multi-core processor

Philippe Morey-Chaisemartin, Eric Beisser

Proceedings Volume 8701, Photomask and Next-Generation Lithography Mask Technology XX; 87010M (2013) https://doi.org/10.1117/12.2028314
Event: Photomask and NGL Mask Technology XX, 2013, Yokohama, Japan

Abstract

Designing a fully new 256 cores processor is a great challenge for a fabless startup. In addition to all architecture, functionalities and timing issues, the layout by itself is a bottleneck due to all the process constraints of a 28nm technology. As developers of advanced layout finishing solutions, we were involved in the design flow of this huge chip with its 3 billions transistors. We had to face the issue of dummy patterns instantiation with respect to design constraints. All the design rules to generate the “dummies” are clearly defined in the Design Rule Manual, and some automatic procedures are provided by the foundry itself, but these routines don’t take care of the designer requests. Such a chip, embeds both digital parts and analog modules for clock and power management. These two different type of designs have each their own set of constraints. In both cases, the insertion of dummies should not introduce unexpected variations leading to malfunctions. For example, on digital parts were signal race conditions are critical on long wires or bus, introduction of uncontrolled parasitic along these nets are highly critical. For analog devices such as high frequency and high sensitivity comparators, the exact symmetry of the two parts of a current mirror generator should be guaranteed. Thanks to the easily customizable features of our dummies insertion tool, we were able to configure it in order to meet all the designer requirements as well as the process constraints. This paper will present all these advanced key features as well as the layout tricks used to fulfill all requirements.

Citation Download Citation

Philippe Morey-Chaisemartin and Eric Beisser "Layout finishing of a 28nm, 3 billions transistors, multi-core processor", Proc. SPIE 8701, Photomask and Next-Generation Lithography Mask Technology XX, 87010M (28 June 2013); https://doi.org/10.1117/12.2028314

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Analog electronics

Computer aided design

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