This PDF file contains the front matter associated with SPIE Proceedings Volume 8886, including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

It can no longer be assumed that the lithographic scaling which has previously driven Moore’s Law will lead in the future to reduced cost per transistor. Until recently, higher prices for lithography tools were offset by improvements in scanner productivity. The necessity of using double patterning to extend scaling beyond the single exposure resolution limit of optical lithography has resulted in a sharp increase in the cost of patterning a critical construction layer that has not been offset by improvements in exposure tool productivity. Double patterning has also substantially increased the cost of mask sets. EUV lithography represents a single patterning option, but the combination of very high exposure tools prices, moderate throughput, high maintenance costs, and expensive mask blanks makes this a solution more expensive than optical double patterning but less expensive than triple patterning. Directed self-assembly (DSA) could potentially improve wafer costs, but this technology currently is immature. There are also design layout and process integration issues associated with DSA that need to be solved in order to obtain full benefit from tighter pitches. There are many approaches for improving the cost effectiveness of lithography. Innovative double patterning schemes lead to smaller die. EUV lithography productivity can be improved with higher power light sources and improved reliability. There are many technical and business challenges for extending EUV lithography to higher numerical apertures. Efficient contact hole and cut mask solutions are needed, as well as very tight overlay control, regardless of lithographic solution.

The semiconductor industry drives a lot of efforts in the field of cost reductions and quality improvements. The consequent use of IT tools is one possibility to support these goals. With the extensions of its 150mm Fab to 200mm Robert Bosch increased the systematic use of data analysis and Advanced Process Control (APC).

With the third generation EUV scanner, the NXE:3300B, it is expected that customers will move into volume manufacturing of the devices and processes currently in development. The NXE:3300B has an NA of 0.33 and is positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full transmission. In this presentation we will demonstrate the imaging performance of the NXE:3300B EUV scanner. With the system operating for almost a year now, we will show the main achievements, and present latest status on system performance, with a focus on imaging of customer device applications. For this, a wide range of features have been evaluated for lithographic performance across the field and across wafer. CD performance for 22nm dense and isolated lines, 18nm and 16nm dense lines with off-axis illumination, 24nm contact holes, as well as performance of customer device structures for 10nm node will be discussed and benchmarked against the current ArF immersion capability. The benefits of EUV for critical customer applications will be discussed, showing excellent imaging results for 2D features and the extension capability to 13nm half pitch and beyond. This demonstrates the capability of EUV to bring the single exposure resolution limit well below what can be achieved with complex multi-patterning techniques on ArFi. The benefit of off-axis illumination usage for process window enhancement at challenging resolutions will be assessed. The influence of mask 3D induced best focus difference on the overlapping depth of focus will also be addressed and compared to current ArFi performance. Furthermore a budget verification will be presented showing CD and contrast budgets for a selection of lithographic features, such as 22nm dense and isolated LS. The contribution of the resist process and the mask will be discussed as well. Finally an outlook will be given to future NA 0.33 systems with improved subsystem performance and full pupil flexibility for off-axis illuminations.

Heated tips offer the possibility to create arbitrary high-resolution nanostructures by local decomposition and evaporation of resist materials. Turnaround times of minutes are achieved with this patterning method due to the high-speed direct-write process and an in-situ imaging capability. Dense features with 10 nm half-pitch can be written into thin films of organic resists such as self-amplified depolymerization (SAD) polymers or molecular glasses. The patterning speed of tSPL has been increased far beyond usual scanning probe lithography (SPL) technologies and approaches the speed of Gaussian shaped electron beam lithography (EBL) for <30 nm resolution. A single tip can write complex patterns with a pixel rate of 500 kHz and a linear scan speed of 20 mm/s. Moreover, a novel scheme for stitching was developed to extend the patterning area beyond the ≤100 μm range of the piezo stages. A stitching accuracy of 10 nm is obtained without the use of markers. Furthermore, the patterning depth can be controlled independently and accurately (~1 nm) at each position. Thereby, arbitrary 3D structures can be written in a single step. Finally, we demonstrated an all-dry tri-layer pattern transfer concept to create high aspect ratio structures in silicon. Dense fins and trenches with 27 nm half-pitch and a line edge roughness (LER) below 3nm (3σ) have been fabricated.

Overlay specifications are tightening with each lithography technology node. As a result, there is a need to improve overlay control methodologies to make them more robust and less time- or effort-consuming, but without any compromise in quality. Two concepts aimed at improving the creation of scanner grid recipes in order to meet evertightening overlay specifications are proposed in this article. Simulations will prove that these concepts can achieve both goals, namely improving overlay control performance and reducing the time and effort required to do so. While more studies are needed to fine-tune the parameters to employ, the trends presented in this paper clearly show the benefits.

Process margin is getting critical in the present node shrinkage scenario due to the physical limits reached (Rayleigh’s criterion) using ArF lithography tools. K1 is used to its best for better resolution and to enhance the process margin (28nm metal patterning k1=0.31). In this paper, we would like to give an overview of various contributors in the advanced technology nodes which limit the process margins and how the challenges have been tackled in a modern foundry model. Advanced OPC algorithms are used to make the design content at the mask optimum for patterning. However, as we work at the physical limit, critical features (Hot-spots) are very susceptible to litho process variations. Furthermore, etch can have a significant impact as well. Pattern that still looks healthy at litho can fail due to etch interactions. This makes the traditional 2D contour output from ORC tools not able to predict accurately all defects and hence not able to fully correct it in the early mask tapeout phase. The above makes a huge difference in the fast ramp-up and high yield in a competitive foundry market. We will explain in this paper how the early introduction of 3D resist model based simulation of resist profiles (resist top-loss, bottom bridging, top-rounding, etc.,) helped in our prediction and correction of hot-spots in the early 28nm process development phase. The paper also discusses about the other overall process window reduction contributors due to mask 3D effects, wafer topography (focus shifts/variations) and how this has been addressed with different simulation efforts in a fast and timely manner.

EUV lithography performance is improved significantly by optimizing and fine-tuning of the EUV mask. The EUV mask is an active element of the scanner optical system influencing main lithographic figure of merits such as image contrast, critical dimension uniformity (CDU), focus and overlay. The mask stack consists of Mo/Si multilayer acting as a bright field and a patterned absorber stack. In this work we will concentrate on investigation of EUV absorber. Absorber topography that is pronounced compared to the imaging wavelength of 13.5 nm, will give rise to various mask 3d effects such as shadowing or dependence of CD on feature orientation, best focus shift of different resolution structures, etc. Light interference in the absorber layer results in swinging behavior of various lithography metrics as function of the absorber height. Optimization of the mask absorber allows mitigating mask 3d effects and improving imaging performance. In particular, reduction of the absorber height mitigates the shadowing effect and relaxes requirements on Optical Proximity Correction (OPC), but can result in smaller Process Window due to lower imaging contrast and larger best focus shifts. In this work we will show results of an experimental approach to absorber height optimization. A special mask with 27 different absorber heights in the range 40-70 nm is manufactured by Toppan Photomasks. EUV reflectivity spectra are measured for the different absorber heights and an experimental swing curve is constructed. For each absorber height various resolution features are present on the mask. Lines of 27 nm and 22 nm are imaged on the wafer using the ASML EUV scanner NXE:3300B with an NA of 0.33. The experimental CD swing curve is constructed as well as HV change as a function of absorber height. The impact of the absorber height on Exposure Latitude (EL) and Dose to Size (D2S) is investigated. EL improves with increasing absorber height in some cases, however there is no clear EL gain for a 70 nm absorber compared to for example 52 nm absorber. D2S does show a clear trend through absorber height. In particular, D2S can be reduced by absorber height reduction: e.g. for 52 nm absorber D2S is 5% or 1 mJ/cm2 smaller compared to 70 nm. The experimental results are used for calibration and verification of rigorous mask 3d simulations. This knowledge is crucial for accurate OPC of production masks and allows for accurate litho simulations of EUV user cases as a basis for lithography roadmaps towards High Volume Manufacturing and High NA EUV.

This paper presents a detailed mask stack modeling based on experimental actinic characterization of the EUV mask stack. A dedicated mask has been fabricated with line/space gratings down to 40nm half-pitch (at mask level, i.e., 10nm at wafer). Using the Advanced Light Source facility at LBNL extensive reflectometry and diffractometry have been performed. The experimental reflectivity results through incidence angle and through EUV wavelength enable us to model both the multilayer definition, as well as the absorber definition in the simulator. The effective performance of the calibrated mask stack in the simulator is validated against the experimental diffractometry results through incidence angle. The presented experimental mask stack characterization and modeling allows a better definition of the mask stack in the simulation tools to enhance their predictive and precompensation power.

The ability of optical lithography to steadily produce images at increasingly smaller dimension while maintaining pattern fidelity of devices with greater complexity has enabled the success of Moore’s Law. Although 193 nm immersion and double patterning techniques have proven successful in extending optical lithography, the strategies proposed for further extension are too costly to support device manufacturing. As a result, greater focus has been shifted to resolving the challenges hindering extreme ultraviolet lithography (EUVL) adoption as the mainstream lithography solution. While similar to conventional optical lithography, there are unique challenges to EUVL, one of which is the change from transmission masks to the reflective masks required for EUVL. The use of reflective reticles greatly increases complexity of EUV reticle structure when compared to the binary masks used with optical lithography. Maximizing the reflectance an EUV mask requires the use of a multilayer Bragg reflector deposited on a finely polished substrate with a thin absorber film on top used to define the device pattern. Although similar in form to the substrates used in optical lithography, the tolerances on figure, surface finish, and defects are significantly more stringent for EUV substrates. Control of aberrations and maintaining pattern fidelity places tight constraints on the flatness and roughness of the EUV substrate; imperfections and particles can result in printable defects. The Bragg reflector of the EUV mask consists of 40 to 50 Si/Mo bi-layers deposited using an ion beam deposition tool. This film stack must be deposited to meet the reflectivity and uniformity requirements of the exposure tool and must be completely free of defects. The absorber film is typically a tantalum-based nitride layer selected for its ability to absorb EUV radiation and maintain thermal stability. The thickness and morphology of this film must be tightly controlled to enable use as the patterning film for the device. In addition to the increase in complexity of the mask, introduction of EUVL requires infrastructure development of new substrate, mask blank, and finished reticle inspection tools and techniques for handling and storage of a mask without a pellicle. This paper will highlight recent advances in the ability to produce pilot line quality EUV mask blanks to meet the near-term requirements and review the existing technology gaps which must be closed to extend the current capability to meet HVM needs. A special focus will be put on substrate and mask blank defect densities; other process and infrastructure challenges will also be discussed.

Positive-tone poly(methyl methacrylate) (PMMA) e-beam resists have already been applied for decades in electron beam lithography. While these resists are characterised by high process stability, their sensitivity, contrast and plasma etch stability must be regarded as comparatively low. A significant improvement of sensitivity and plasma etch stability can be achieved with e-beam resists on the basis of α-methyl styrene α-chloromethacrylate copolymers (e.g. ZEP 520) that are also perfect candidates for preparation of undercut architectures for lift-off applications. Main disadvantage of these resists however is a low commercial availability. On the other hand, chemical amplified resist (CAR) systems are known which show a one order of magnitude higher sensitivity than conventional e-beam resists, but the resolution of these resists is limited due to diffusion processes inherent to the chemical amplification.

The semiconductor maskmaking industry imposes challenging requirements for the uniformity of critical dimensions (CD) and placement error. In electron beam lithography (EBL), electrons backscatter from the resist and substrate, reach the bottom of objective lens and come back to the resist, causing undesirable exposure and charging far away from the point of exposure. This fogging effects both CD variation and placement accuracy in EBL. The Monte Carlo software CHARIOT was upgraded to be capable of simulating this fogging effect. The results of simulations are presented. It was found that Gaussian approximation is sufficient; the approximation parameters were found for various working distances. The results were used for the correction of charging placement error. Fogging is one of the major contributing factors to the charging placement error; the DISPLACE software tool predicts the displacement map for any layout, which allows for the correction of placement error in maskmaking.

Proximity Effects in electron beam lithography impact feature dimensions, pattern fidelity and uniformity. These effects are addressed using a mathematical model representing the radial exposure intensity distribution induced by a point electron source, commonly named as the Point Spread Function (PSF). PSF models are usually employed for predicting and compensating for effects up to 15μm. It is well known that there are also some process related phenomena that impact pattern uniformity that have a longer range, namely CMP effects, fogging, etc. Performing proximity effects corrections can result in lengthy run times as file size and pattern densities continue to increase exponentially per technology node. Running corrections for extreme long range phenomena becomes computational and file size prohibitive. Nevertheless, since extreme long range may reach up several millimeters, and new technology nodes require a high level of precision, a strategy for predicting and compensating these phenomena is crucial. In this paper a set of test patterns are presented in order to verify and calibrate the so called extreme long range effects in the electron beam lithography. Moreover, a strategy to compensate for extreme long range effects based on the pattern density is presented. Since the evaluation is based on a density map instead of the actual patterns, the computational effort is feasible. The proposed method may be performed off-line (in contrast to machine standard in-line correction). The advantage of employing off-line compensation relies on enhancing the employ of dose and/or geometry modulation. This strategy also has the advantage of being completely decoupled from other e-beam writer’s internal corrections (like Fogging Effect Correction - FEC).

The need for an actinic wavelength AIMS™ EUV tool by 2014 has been defined by SEMATECH due to the challenges associated with EUV mask manufacture and defectivity. The AIMS™ EUV development project began in June of 2011 as a collaboration between ZEISS and the SEMATECH EUVL Mask Infrastructure (EMI) consortium. The project remains on track to meet the first commercial tool shipment in September 2014. The current design status of the system after two years as well as recent progress in the prototype build will be presented.

Upcoming semiconductor technology nodes will still be based on optical lithography by ArF water immersion technology because there are still too many open issues preventing extreme ultraviolet (EUV) lithography from being introduced into high volume production. Several kinds of multi-patterning technology are considered to overcome the optical resolution issue by 193nm high NA illumination and still achieve <32nm half-pitch. Mask registration metrology must be adapted to provide useful and comprehensive data on the mask contribution to wafer overlay.

The ZEISS AIMS™ measurement system has been established for many years as the industry standard for qualifying the printability of mask features based on the aerial image. Typical parameters in determining the printability of a feature are the critical dimension (CD) and intensity deviations of the feature or region of interest with respect to the nominal. While this information is critical to determine if the feature will pass printability, it gives little insight into why the feature failed. For instance, determining if the failure occurs due to the quartz level deviating from that of the nominal height can be problematic. Atomic force microscopy (AFM) is commonly used to determine such physical dimensions as the quartz etch depth or height and sidewall roughness for verification purposes and to provide feedback to front end processes. In addition the AFM is a useful tool in monitoring and providing feedback to the repair engineers as the depth of the repair is one of the many critical parameters which must be controlled in order to have a robust repair process. In collaboration with Photronics nanoFab, we have previously shown the Bossung plot obtained from the AIMS™ aerial image of a feature can be used to determine if the quartz level of a repaired region is above or below the nominal value. This technique can further be used to extract the etch time associated with the nominal quartz height in order to optimize the repair process. The use of this method can be used in lieu of AFM, effectively eliminating the time and effort associated with performing additional metrology steps in a separate system. In this paper we present experimental results supporting the technique and its applicability.

We report on Mueller Matrix spectroscopic ellipsometry (MM-SE) to examine undesired asymmetries in structural parameters, i.e. line edge roughness (LER). The investigation was done on a photomask containing line space arrays with intentionally modulated line edges. The Mueller Matrix (MM) elements were measured within the complete azimuth angle range (0 - 360°) and a wavelength range from 300 nm to 980 nm. The results are presented in polar coordinates with the azimuth angle and wavelength as the angular and radial coordinate, respectively. It was found that LER significantly impacts the MM elements, which is indicated by the increase of the isotropic character of the array. The experimental data are confirmed by Rigorous Coupled Wave Analysis (RCWA) simulations on perturbed arrays. Based on RCWA the impact of LER amplitudes in the nm range is determined. It was found that both deviation of critical dimension (CD) and LER amplitude impact the MM elements. Based on the intensity ratios of the elements and their spectral distribution both errors create a characteristic finger print, which allows to separate them. Finally, the required measurement precision for LER in the nm range is estimated at 0.001. This precision is challenging but achievable with today’s metrology.

Progress in IC technologies is usually based on costly improvements of process equipment. An alternative path is to look into opportunities based on the engineering disclosures, which can have a lot of potential in the Design-for- Manufacturing domain. This paper discusses six examples of such disclosures, filed in the 2010-2012 timeframe.

The 20nm Metal1 layer, based on ARM standard cells, has a 2D design with minimum pitch of 64nm. This 2D design requires a Litho-Etch-Litho-Etch (LELE) double patterning. The whole design is divided in 2 splits: Me1A and Me1B. But solution of splitting conflicts needs stitching at some locations, what requires good Critical Dimension (CD) and overlay control to provide reliable contact between 2 stitched line ends. ASML Immersion NXT tools are aimed at 20 and 14nm logic production nodes. Focus control requirements become tighter, as existing 20nm production logic layouts, based on ARM, have about 50-60nm focus latitude and tight CD Uniformity (CDU) specifications, especially for line ends. IMEC inspected 20nm production Metal1 ARM standard cells with a Negative Tone Development (NTD) process using the Process Window Qualification-like technique experimentally and by Brion Tachyon LMC by simulations. Stronger defects were found thru process variations. A calibrated Tachyon model proved a good overall predictability capability for this process. Selected defects are likely to be transferred to hard mask during etch. Further, CDU inspection was performed for these critical features. Hot spots showed worse CD uniformity than specifications. Intra-field CDU contribution is significant in overall CDU budget, where reticle has major impact due to high MEEF of hot spots. Tip-to-Tip and tip-to-line hot spots have high MEEF and its variation over the field. Best focus variation range was determined by best focus offsets between hot spots and its variation within the field.

As Moore’s Law continues its relentless march toward ever smaller geometries on wafer, lithographers who had been relying on the implementation of a solution using EUV lithography are faced with increasing challenges to meet requirements for printing sub-2x nm half-pitch (HP). The available choices rely on 193 nm DUV immersion lithography, but with decreasing k₁ values and thus shrinking process windows. To overcome these limitations, two techniques such as inverse lithography technology (ILT) and source mask optimization (SMO) were introduced by computational OPC scheme. From a mask inspection viewpoint, the impact of both ILT and SMO is similar – both result in photomasks that have a large quantity of sub-resolution assist features (SRAFs). These SRAFs are challenging for mask-makers to pattern with high fidelity and accuracy across a full-field mask, and thus mask inspection is challenged to maintain a high sensitivity level on primary mask features while not suffering from a high nuisance detection rate on the SRAF features. To solve this particular issue, new inspection approach was developed by using computational image calibration based wafer scanner simulation. This paper will be described the new capabilities, which analyzes the aerial image to differentiate between printing and non-printing features, and applying the appropriate sensitivity threshold. All analysis will be shown comparing results with and without the new capabilities, with an emphasis on inspectability improvements and nuisance defect reduction to improve mask cycle time.

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.