KEYWORDS: Image compression, LCDs, Image quality, Clocks, Computer programming, RGB color model, Video, Very large scale integration, Video compression, Visualization
An LCD Driver with on-chip frame buffer and 3 times image compression codec reaching visually lossless image quality
is presented. The frame buffer compression codec can encode and decode up to eight pixels in one clock cycle.
Integrating a whole frame buffer with RGB=888 bits into the display driver sharply reduces power dissipated between
the IO pad and PCB board at a cost of 50% IC die area increase. The existing working chip (STE2102, a ram-less LCD
Driver with die size of 170mm x 12mm) is manufactured by ST Micro 0.18μm high voltage CMOS process. A new chip
design with on-chip frame buffer SRAM and 3 times compression codec supporting QVGA (320x240) is completed
which reduces the frame buffer SRAM density and area by a factor of ~3.0 times and cuts the power consumption of the
on-chip SRAM frame buffer by ~9.0 times of which 3 times is contributed by less capacitive bit line load and another 3
times from data rate reduction from image compression. The compression codec having 25K gates in encoder and 10K
in decoder accepts both YUV and RGB color formats. An on-chip color-space-conversion unit converts the
decompressed YUV components with 420, 422 and 444 formats to be RGB format before driving out to be displayed.
The high image quality is achieved by applying some patented proprietary compression algorithms including accurate
prediction in DPCM, a Golomb-Rice like VLC coding with accurate predictive divider and an intelligent bit rate
distribution control.
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