We present our versatile simulation framework for the schematic-driven and layout-aware design of photonic integrated circuits (PICs) realizing a fast and user-friendly design flow for large-scale PICs comprising passive and active building blocks (BBs). We show how the seamless interaction of circuit simulation with photonic layout design tools allows to specify and utilize directly physical locations and orientations of BBs of standardized process design kits (PDKs). We demonstrate how to combine graphical schematic capture and automated waveguide routing, and discuss by means of typical design applications how an optimized design flow can speed-up the virtual prototyping of complex PICs and optoelectronic applications.
S. Mingaleev, A. Richter, E. Sokolov, S. Savitzki, A. Polatynski, J. Farina, and I. Koltchanov, "Rapid virtual prototyping of complex photonic integrated circuits using layout-aware schematic-driven design methodology," Proc. SPIE 10107, Smart Photonic and Optoelectronic Integrated Circuits XIX, 1010708 (Presented at SPIE OPTO: February 01, 2017; Published: 20 February 2017); https://doi.org/10.1117/12.2252001.
Conference Presentations are recordings of oral presentations given at SPIE conferences and published as part of the conference proceedings. They include the speaker's narration along with a video recording of the presentation slides and animations. Many conference presentations also include full-text papers. Search and browse our growing collection of more than 14,000 conference presentations, including many plenary and keynote presentations.