This invited talk reviews recent technology advances in our three generations of low-power CMOS coherent digital signal processor (DSP) implemented with 40, 20, and 16-nm CMOS technologies, with highlights on its functional integration, adaptation, and design optimization for power-efficiency CMOS DSP implementation. The latest 16-nm third-generation (Gen3) DSP implementation achieves sub-10-watt per 100 Gb/s coherent transmission in both 100G DP-QPSK and 200G DP-16QAM transport modes for the first time, and experimentally confirms its trade-off between transmission performance and power dissipations.
Osamu Ishida and Atul K. Srivastava, "Recent advances in low-power CMOS-coherent digital-signal-processing (DSP) technologies (Conference Presentation)," Proc. SPIE 10130, Next-Generation Optical Communication: Components, Sub-Systems, and Systems VI, 101300I (Presented at SPIE OPTO: February 01, 2017; Published: 26 April 2017); https://doi.org/10.1117/12.2253183.5387787105001.
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