Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.
Honggoo Lee, Sangjun Han, Jaeson Woo, Junbeom Park, Changrock Song, Fatima Anis, Pradeep Vukkadala, Sanghuck Jeon, DongSub Choi, Kevin Huang, Hoyoung Heo, Mark D. Smith, and John C. Robinson, "Patterned wafer geometry grouping for improved overlay control," Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 101450O (Presented at SPIE Advanced Lithography: February 28, 2017; Published: 28 March 2017); https://doi.org/10.1117/12.2257834.
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