The layout design for silicon photonics can be complicated and usually have edges with arbitrary angles. The critical dimension can be less than 100 nm, requiring the layouts to be OPCed in order to have large enough process windows for high volume manufacturing. However, the well-established CMOS-orientated IC industry OPC tools for advanced nodes can only handle Manhattan designs in which the Manhattan style polygons with edges of 0°, 90° or 45° to the reference direction. Silicon photonics layouts need to be discretized in order to use the existing OPC tools. From optical performance point of view, the design grid is expected to be as small as possible and it is usually from 1 nm to 5 nm. However, the design grid has never been optimized based on the OPC performance.
In this paper, we demonstrate the impacts of design grid on the OPC performance. Design grid for silicon photonics is not always the smaller the better anymore. Our study shows that small 2D designs require large design grids while smooth curves with large radius require small design grids.
We proposed a novel design-based discretization algorithm to convert a non-Manhattan style layout to an OPC-friendly Manhattan style layout. Simulation results show that the pattern fidelity is optimized for both small 2D patterns and smooth curves.
Wenhui Wang, Xiaochi Chen, Lei Sun, Alexander Y. Piggott, Jelena Vuckovic, and Jongwook Kye, "Design grid optimization for OPC of silicon photonics (Conference Presentation)," Proc. SPIE 10147, Optical Microlithography XXX, 1014710 (Presented at SPIE Advanced Lithography: March 02, 2017; Published: 26 April 2017); https://doi.org/10.1117/12.2261428.5402356387001.
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