A typical new IC design has millions of layout configurations, not seen on previous product or test chip designs.
Knowing the disposition of each and every configuration, problematic or not, is the key to optimizing design for yield. In
this paper, we present a method to systematically characterize the configuration coverage of any layout. Coverage can be
compared between designs, and configurations for which there is a lack of coverage can also be computed. When
combined with simulation, metrology, and defect data for some configurations, graph search and machine learning
algorithms can be applied to optimize designs for manufacturing yield.
Vito Dai, Edward Kah Ching Teoh, Ji Xu, and Bharath Rangarajan, "Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning," Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014808 (Presented at SPIE Advanced Lithography: March 01, 2017; Published: 3 April 2017); https://doi.org/10.1117/12.2262146.
Conference Presentations are recordings of oral presentations given at SPIE conferences and published as part of the proceedings. They include the speaker's narration with video of the slides and animations. Most include full-text papers. Interactive, searchable transcripts and closed captioning are now available for 2018 presentations, with transcripts for prior recordings added daily.
Search our growing collection of more than 16,000 conference presentations, including many plenaries and keynotes.