As pitch scaling is becoming constrained not only by lithographic resolution limits but alos by fundamental device and interconnect challenges the semiconductor industry has turned to cell-height reduction as a means of achieving competitive area scaling. The risk in using cell-height reduction to compensate for insufficient pitch scaling is that place- and-route inefficiencies caused by wiring congestion at the block level of the design can easily eliminate any area scaling gains made at the cell level of the design. This paper shows how careful cell-architecture optimization, physical design methodology changes, and place-and-route innovations have led to competitive block level area scaling for 7nm technology nodes and beyond. Data is presented to show that an entire node’s worth of scaling can be achieved through these comprehensive design-technology co-optimization efforts.
L. Liebmann, V. Gerousis, Paul Gutwin, Xuelian Zhu, and Jan Petykiewicz, "Exploiting regularity: breakthroughs in sub-7nm place-and-route," Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480F (Presented at SPIE Advanced Lithography: March 02, 2017; Published: 28 March 2017); https://doi.org/10.1117/12.2259981.
Conference Presentations are recordings of oral presentations given at SPIE conferences and published as part of the conference proceedings. They include the speaker's narration along with a video recording of the presentation slides and animations. Many conference presentations also include full-text papers. Search and browse our growing collection of more than 12,000 conference presentations, including many plenary and keynote presentations.