We demonstrate a tool which can function as an interface between VLSI designers and process-technology engineers
throughout the Design-Technology Co-optimization (DTCO) process. This tool uses a Monte Carlo algorithm on the
output of lithography simulations to model the frequency of fail mechanisms on wafer. Fail mechanisms are defined
according to process integration flow: by Boolean operations and measurements between original and derived shapes.
Another feature of this design rule optimization methodology is the use of a Markov-Chain-based algorithm to perform a
sensitivity analysis, the output of which may be used by process engineers to target key process-induced variabilities for
improvement. This tool is used to analyze multiple Middle-Of-Line fail mechanisms in a 10nm inverter design and identify
key process assumptions that will most strongly affect the yield of the structures. This tool and the underlying algorithm
are also shown to be scalable to arbitrarily complex geometries in three dimensions. Such a characteristic which is
becoming more important with the introduction of novel patterning technologies and more complex 3-D on-wafer
Eric Eastman, Dureseti Chidambarrao, Werner Rausch, Rasit O. Topaloglu, Dongbing Shao, Ravikumar Ramachandran, and Matthew Angyal, "Identification and sensitivity analysis of a correlated ground rule system (design arc)," Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480I (Presented at SPIE Advanced Lithography: March 02, 2017; Published: 4 April 2017); https://doi.org/10.1117/12.2258002.
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