Transistor scaling has transitioned from wavelength scaling to multi-patterning techniques, due to the resolution limits of immersion of immersion lithography. Deposition and etch have enabled scaling in the by means of SADP and SAQP. Spacer based patterning enables extremely small linewidths, sufficient for several future generations of transistors. However, aligning layers in Z-direction, as well as aligning cut and via patterning layers, is becoming a road-block due to global and local feature variation and fidelity. This presentation will highlight the impact of deposition and etch on this feature alignment (EPE) and illustrate potential paths toward lowering EPE using material engineering.
Regina Freed, Uday Mitra, and Ying Zhang, "Impact of materials engineering on edge placement error (Conference Presentation)," Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 1014905 (Presented at SPIE Advanced Lithography: February 28, 2017; Published: 27 April 2017); https://doi.org/10.1117/12.2261107.5402356438001.
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