The "internet of everything" envisions trillions of connected objects loaded with high-bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. From the computational viewpoint, the challenge is formidable and can be addressed only by pushing computing fabrics toward massive parallelism and brain-like energy efficiency levels. CMOS technology can still take us a long way toward this goal, but technology scaling is losing steam. Energy efficiency improvement will increasingly hinge on architecture, circuits, design techniques such as heterogeneous 3D integration, mixed-signal preprocessing, event-based approximate computing and non-Von-Neumann architectures for scalable acceleration.
Luca Benini, "Smart integrated microsystems: the energy efficiency challenge (Plenary Presentation)," Proc. SPIE 10248, Nanotechnology VIII, 1024802 (Presented at SPIE Microtechnologies: May 08, 2017; Published: 16 June 2017); https://doi.org/10.1117/12.2268453.5470920623001.
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