From Event: SPIE Optical Engineering + Applications, 2017
In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.
Saptarshi Mandal, Anchal Agarwal, Elaheh Ahmadi, K. Mahadeva Bhat, Matthew A. Laurent, Stacia Keller, and Srabanti Chowdhury, "Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer," Proc. SPIE 10381, Wide Bandgap Power Devices and Applications II, 1038108 (Presented at SPIE Optical Engineering + Applications: August 08, 2017; Published: 23 August 2017); https://doi.org/10.1117/12.2279435.
Conference Presentations are recordings of oral presentations given at SPIE conferences and published as part of the conference proceedings. They include the speaker's narration along with a video recording of the presentation slides and animations. Many conference presentations also include full-text papers. Search and browse our growing collection of more than 14,000 conference presentations, including many plenary and keynote presentations.