Practical machine learning (ML) techniques are being deployed, at an accelerated pace, in an expanding set of application domains. The newsworthy examples in games strategy, image recognition, automated translation and autonomous driving are only the tip of the iceberg of a massive revolution in industrial manufacturing. Semiconductor IC design and manufacturing are also starting to see a number of ML applications, albeit of limited scope. In this work we present both a novel computational tool for ML of physical design layout styles (constructs, patterns) and also a general technical framework for the implementation of ML solutions across the design to mask to silicon chain.
ML applications derive their mathematical foundations from Computational Learning Theory, which establishes “learning” as a computational process. The quantitative characterization of the learnability space and its associated Vapnik-Chervonenkis, (VC) dimension, is therefore a pre-requisite of any meaningful ML application. Various types of geometric constructs in the 3D Euclidian space of physical design layouts provide an ideal learnability domain. Specifically, the entire set of generalized Design Rules, silicon retargeting, Optical proximity Correction (OPC), post-OPC verification (ORC) and mask manufacturing constraints (MRC) can be demonstrated to be in a learnable set. This means that, given a suitable feature extraction model, classifiers systems can be built to perform data analytics and optimization, with a quantifiably higher performance (in terms of speed and scale) than any of the currently used engineering-based heuristics. Additionally layout styles, particularly the ones generated by Place-and-Route (P&R) tools and even manual layout for custom blocks are amenable to automated learning (and subsequent parametric-space optimization).
Two complete examples in the Design to Mask flow, for advanced technology node applications will be used to validate the ML methodological framework and to illustrate extendibility to other areas, such as process and fab flow optimization.
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Luigi Capodieci, "Machine learning of IC layout "styles" for Mask Data Processing verification and optimization (Conference Presentation)," Proc. SPIE 10451, Photomask Technology, 104510B (Presented at SPIE Photomask Technology and EUV Lithography: September 11, 2017; Published: 16 October 2017); https://doi.org/10.1117/12.2282885.5613169408001.
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