Sub-Resolution Assist Features (SRAF) are widely used for Process Window (PW) enhancement in computational
lithography. Rule-Based SRAF (RB-SRAF) methods work well with simple designs and regular repeated patterns, but
require a long development cycle involving Litho, OPC, and design-technology co-optimization (DTCO) engineers.
Furthermore, RB-SRAF is heuristics-based and there is no guarantee that SRAF placement is optimal for complex
patterns. In contrast, the Model-Based SRAF (MB-SRAF) technique to construct SRAFs using the guidance map is
sufficient to provide the required process window for the 32nm node and below. It provides an improved lithography
margin for full chip and removes the challenge of developing manually complex rules to assist 2D structures. The
machine learning assisted SRAF placement technique developed on the ASML Brion Tachyon platform allows us to
push the limits of MB-SRAF even further. A Deep Convolutional Neural Network (DCNN) is trained using a
Continuous Transmission Mask (CTM) that is fully optimized by the Tachyon inverse lithography engine. The neural
network generated SRAF guidance map is then used to assist full-chip SRAF placement. This is different from the
current full-chip MB-SRAF approach which utilizes a guidance map of mask sensitivity to improve the contrast of
optical image at the edge of lithography target patterns. We expect that machine learning assisted SRAF placement can
achieve a superior process window compared to the MB-SRAF method, with a full-chip affordable runtime significantly
faster than inverse lithography. We will describe the current status of machine learning assisted SRAF technique and
demonstrate its application on the full chip mask synthesis and how it can extend the computational lithography
Shibing Wang, Jing Su, Quan Zhang, Weichun Fong, Dezheng Sun, Stanislas Baron, Cuiping Zhang, Chenxi Lin, Been-Der Chen, Rafael C. Howell, Stephen D. Hsu, Larry Luo, Yi Zou, Yen-Wen Lu, and Yu Cao, "Machine learning assisted SRAF placement for full chip," Proc. SPIE 10451, Photomask Technology, 104510D (Presented at SPIE Photomask Technology and EUV Lithography: September 11, 2017; Published: 16 October 2017); https://doi.org/10.1117/12.2283493.
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