The first generation of silicon photonic products is now commercially available. While silicon photonics possesses key economic advantages over classical photonic platforms, it has yet to become a commercial success because these advantages can be fully realized only when high-volume testing of silicon photonic devices is made possible. We discuss the costs, challenges, and solutions of photonic chip testing as reported in the recent research literature. We define and propose three underlying paradigms that should be considered when creating photonic test structures: Design for Fast Coupling, Design for Minimal Taps, and Design for Parallel Testing. We underline that a coherent test methodology must be established prior to the design of test structures, and demonstrate how an optimized methodology dramatically reduces the burden when designing for test, by reducing the needed complexity of test structures.
Robert Polster, Liang Yuan Dai, Michail Oikonomou, Qixiang Cheng, Sebastien Rumley, and Keren Bergman, "Challenges and solutions for high-volume testing of silicon photonics," Proc. SPIE 10537, Silicon Photonics XIII, 1053703 (Presented at SPIE OPTO: January 29, 2018; Published: 22 February 2018); https://doi.org/10.1117/12.2292235.
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