With ever shrinking feature sizes, the IC industry continues to seek high quality lithography that includes low line edge roughness (LER), high resolution, and straight pattern profiles with solutions to pattern forbidden pitch and hot spots. This paper will discuss a new approach that is proposed to improve these desired characteristics up to the system’s stochastic limit.
The nature of LER is stochastic, which can be considered a barrier of patterning resolution. With this barrier, how can engineers take advantage of minimizing stochastic effects to achieve minimum LER and best resolution all while approaching the limitation of intrinsic roughness? In order to understand these effects, a new criterion is proposed that describes the region where variability can occur, called stochastic area thickness (SAT). The SAT of the resist is calculated from optical imaging and resist contrast curve (including acid diffusion effects). This SAT value will be used to develop a second criterion that accounts for effects only seen during the resist developing process, developed stochastic area thickness (DSAT). The DSAT value can be used as an approximation of the actual stochastic effects in the patterning process. Since pattern formation depends on DSAT value, the number of printable die (NPD), or printability, is chosen as DSAT criteria. A variety of lithography conditions with a variety of SAT values were analyzed using this new approach. The results indicate that DSAT correlates well to printability, LER and pattern profile. However, the approaches to minimize DSAT may contradict methods typically used for conventional lithography. Fortunately, for conventional lithography, the DSAT value has a large margin for improvement, and process and material recommendations are proposed.
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