Traditionally, optical proximity correction (OPC) on cell array patterns in memory layout uses simple bias rules to correct hierarchically-placed features, but requires intensive, rigorous lithographic simulations to maximize the wafer process latitude. This process requires time-consuming procedures to be performed on the full chip (excluding the cell arrays) to handle unique cell features and layout placements before (and even sometimes after) OPC. The time required limits productivity for both mask tapeouts and the wafer process development. In this paper, a new cell array OPC flow is introduced that reduces turnaround-time for mask tapeouts from days to hours, while maintaining acceptable OPC quality and the perfect geometric consistency on the OPC output that is critical for memory manufacturing. The flow comprises an effective sub-resolution assist features (SRAFs) insertion and OPC for both the cell array and the peripheral pattern areas. Both simulation and experimental results from actual wafer verification are discussed.
Ahmed Seoud, Sherif Hany, Juhwan Kim, Jebum Yoon, Boram Jung, Sang-Jin Oh, Byoung-Sub Nam, Seyoung Oh, and Chan-Ha Park, "Model based cell-array OPC development for productivity improvement in memory device fabrication," Proc. SPIE 10587, Optical Microlithography XXXI, 105870K (Presented at SPIE Advanced Lithography: February 28, 2018; Published: 20 March 2018); https://doi.org/10.1117/12.2297638.
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