As the computational requirements for post tape out (PTO) flows increase at the 7nm and below technology nodes, there is a need to increase the scalability of the computational tools in order to reduce the turn-around time (TAT) of the flows. Utilization of design hierarchy has been one proven method to provide sufficient partitioning to enable PTO processing. However, as the data is processed through the PTO flow, its effective hierarchy is reduced. The reduction is necessary to achieve the desired accuracy. Also, the sequential nature of the PTO flow is inherently non-scalable. To address these limitations, we are proposing a quasi-hierarchical solution that combines multiple levels of parallelism to increase the scalability of the entire PTO flow. In this paper, we describe the system and present experimental results demonstrating the runtime reduction through scalable processing with thousands of computational cores.
Hien T. Vu, Soohong Kim, James Word, and Lynn Y. Cai, "A novel processing platform for post tape out flows," Proc. SPIE 10587, Optical Microlithography XXXI, 105870R (Presented at SPIE Advanced Lithography: February 28, 2018; Published: 20 March 2018); https://doi.org/10.1117/12.2297240.
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