In imec predictive N5 technology platform (poly pitch 42nm, metal pitch 32nm), enabling cell height reduction from 6 to 5 tracks constitutes an interesting opportunity to reduce area of digital IP-blocks without increasing wafer cost. From a physical point of view, the two main challenges of reducing the number of tracks are posed by the increased difficulty of completing inter-cell connections in standard cell design, and by increased pin density that makes more challenging for the router to maintain high placement densities. Both these issues can potentially result into cell and chip area enlargement, thus mitigating or canceling the benefits of moving to 5-Tracks. In this study this side effect was avoided through a careful Design-Technology Co-Optimization approach (DTCO) , where a set of design arcs was used in conjunction with an EUV compatible ruleset that allowed efficient 5-Tracks standard cell design, resulting in final area gains up to 17% that were validated through a commercial state-of-the-art Place and Route (P&R) flow.
L. Matti, V. Gerousis, M. Berekovic, P. Debacker, S. M. Y. Sherazi, D. Milojevic, R. Baert, J. Ryckaert, Ryoung-han Kim, Diederik Verkest, and P. Raghavan, "Efficient place and route enablement of 5-tracks standard-cells through EUV compatible N5 ruleset," Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058803 (Presented at SPIE Advanced Lithography: February 28, 2018; Published: 20 March 2018); https://doi.org/10.1117/12.2297336.
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