Building on previous work for cataloging unique topological patterns in an integrated circuit physical design, a new process is defined in which a risk scoring methodology is used to rank patterns based on manufacturing risk. Patterns with high risk are then mapped to functionally equivalent patterns with lower risk. The higher risk patterns are then replaced in the design with their lower risk equivalents. The pattern selection and replacement is fully automated and suitable for use for full-chip designs. Results from 14nm product designs show that the approach can identify and replace risk patterns with quantifiable positive impact on the risk score distribution after replacement.
Jason P. Cain, Moutaz Fakhry, Piyush Pathak, Jason Sweis, Frank Gennari, and Ya-Chieh Lai, "Applying machine learning to pattern analysis for automated in-design layout optimization
," Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058805 (Presented at SPIE Advanced Lithography: February 28, 2018; Published: 10 April 2018); https://doi.org/10.1117/12.2299492.
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