In order to maintain the scaling trend in logic technology node progression, imec technology nodes started heavily utilizing design technology co-optimization (DTCO) on top of loosen pitch scaling trend to mitigate the burden from steep cost increase and yield challenge. Scaling boosters are adopted to enable DTCO process on top of patterning near its cliff to mitigate the cost increase. As the technology node further proceeds, DTCO also starts facing its cliff, and system technology co-optimization (STCO) is introduced to assist pitch and DTCO scaling to bridge 2-D IC technology to evolutionary technology options such as MRAM, 2.5-D heterogeneous integration, 3-D integration and 3-D IC. EUV is used to further assist pitch and DTCO scaling to maintain low cost with higher yield and faster turn-around-time (TAT). EUV single patterning, multiple patterning and high-NA EUV are considered on top of DTCO and STCO landscape to define imec technology nodes.
Ryoung-han Kim, Yasser Sherazi, Peter Debacker, Praveen Raghavan, Julien Ryckaert, Arindam Malik, Diederik Verkest, Jae Uk Lee, Werner Gillijns, Ling Ee Tan, Victor Blanco, Kurt Ronse, and Greg McIntyre, "IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend," Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880N (Presented at SPIE Advanced Lithography: March 01, 2018; Published: 20 March 2018); https://doi.org/10.1117/12.2299335.
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