During the last several years we have seen an impressive drive in the industry to continue to innovate in order to keep up with the challenging requirements of overlay in multi-patterning processes. A major part of these efforts is spent in opening up of the flexibility in control knobs on process tools (mostly lithography and etch) enabling the high order actuation capability. In order to feed this high order actuation, it has also become important to address the need of input data accuracy, driving up the demand for improved metrology accuracy and sampling. Adding to the complexity, it has also become important to address edge placement error (EPE). EPE is basically the pattern fidelity of a device structure created by a multi-patterning process, defined as the relative displacement of the edges of two features from their intended target position. Here local CD error is an important parameter in addition to overlay. EPE requirements of a "single digit nanometer number" is now a harsh reality in 5nm nodes and below.

In this technical presentation we will review the above developments and remaining gaps in technology (litho and dimensional metrology applications), as well as design and integration. Mitigation of such challenges need a large team effort that is industry-wide and not just limited in litho.

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Kaustuve Bhattacharyya, "Tough road ahead for device overlay and edge placement error," Proc. SPIE 10959, Metrology, Inspection, and Process Control for Microlithography XXXIII, 1095902 (Presented at SPIE Advanced Lithography: February 25, 2019; Published: 26 March 2019); https://doi.org/10.1117/12.2514820.