Critical edge placement margins continue to shrink in advanced designs, Over the years, various methods have been used to quantify the lithographic “process window”, often in terms of allowable CD variation. Ultimately however, what is of most interest is the margin for chip failure, either due to hard pinching, bridging, or pattern collapse of a single layer, or interlayer critical edge placement errors. The latter could include insufficient overlap between layers such as metal and via, or unwanted bridging of patterns between layers. We present here a framework for estimating the failure rate for any individual feature given an assumed manufacturing distribution of primary patterning variables such as dose, focus, mask dimension, and perhaps overlay. If the failure rate for all features within the die is known, then by extension the failure rate for the entire die can be known. Since estimating the process window exhaustively for all in-die locations is not possible, we first identify process window limiting features, then utilize this knowledge to estimate overall die failure rates. This method can account for both systematic failure of an individual feature instance as well as stochastic failure for repeating patterns.

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John Sturtevant, Lianghong Yin, Young Chang Kim, Shumay Shang, Andrew Burbine, Chris Clifford, and Kostas Adam, "Process window-based feature and die failure rate prediction ," Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 109620B (Presented at SPIE Advanced Lithography: February 27, 2019; Published: 20 March 2019); https://doi.org/10.1117/12.2516101.