By adopting the new design of the optics within the scanner, high-NA (0.55NA) EUV lithography enables higher resolution, which will push the EUV single patterning down to pitch 16nm (k1=0.34, the same k1 value as pitch 28nm for 0.33NA EUV single patterning). Therefore, 0.55NA EUVL is projected to print the most critical features of 2nm node (and beyond) logic chips with less patterning steps than 0.33NA EUVL, and is highly expected by the industry. Besides, novel low-n low-k absorber attenuated phase shift masks (low-n attPSMs) are commercially available recently, which have shown substantial imaging, as well as patterning performance improvements both in simulations and experiments. Thus, in this paper, we evaluate the feasibility and limits of logic metal scaling with 0.55NA EUV single pattering using source mask optimization tool, both binary and low-n attPSMs are used to pattern an imec N3 (pitch 28nm, foundry N2 equivalent) random logic metal design and the linear scaled versions (down to pitch 18nm). The impact of design orientations (horizontal vs. vertical) and mask tones (dark field vs. bright field) on patterning fidelity and overall process window is evaluated.

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Dongbo Xu, Ling Ee Tan, Vicky Philipsen, Joerg Zimmermann, and Werner Gillijns, "Feasibility of logic metal scaling with 0.55NA EUV single patterning," Proc. SPIE 12494, Optical and EUV Nanolithography XXXVI, 124940M (Presented at SPIE Advanced Lithography + Patterning: March 01, 2023; Published: 28 April 2023); https://doi.org/10.1117/12.2657983.