Fin depopulation, thinner and taller fins, and the step towards Nanosheet technologies has been helping in maintaining the rhythm of the semiconductor technology roadmap. Nevertheless, further area scaling causes a drastic reduction in active width as well as a challenging routability. On this regard, the Complementary-FET is a strong contender as device for next generation technologies. The stack of p- on n-FETs offers several opportunities for device scaling and optimization. However, it also poses several challenges that need to be carefully analyzed in a design-technology cooptimization framework.

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G. Mirabelli, P. Schuddinck, H.-H. Liu, S. Yang, O. Zografos, S. M. Salahuddin, P. Weckx, G. Hiblot, G. Hellings, and J. Ryckaert, "Design-technology co-optimization overview of CFET architecture," Proc. SPIE 12495, DTCO and Computational Patterning II, 124950M (Presented at SPIE Advanced Lithography + Patterning: March 01, 2023; Published: 28 April 2023); https://doi.org/10.1117/12.2657726.