From Event: SPIE Advanced Lithography + Patterning, 2023
The demand for high-performance semiconductor products has increased with no end in sight since the early days of this industry. This product demand phenomenon has continuously pushed the technological frontier to a moving limit for enhanced performance leading to the need for an ever-thinner die for advanced 3D packaging. Die down to a thickness of 5 µm is feasible. The thin die approach may lead to a heterogenous stack of 50 dies, leading to the highest available performance with an unprecedented form factor. One significant barrier is the fragility of the thin die and its impact on yield, reliability, and costs. A comprehensive crack propagation and thin die fragility model that is rich in both theory and application is presented. In this paper, we show an MPW reticle placement with automation that inserts new and specific crack-stop patterns to mitigate the risk of die wafer fracture. We show this method to address die fracture from both the front and the back sides of the wafer, yielding an authentic 3D approach to crack-stop.
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jaime Bravo, Philippe Morey-Chaisemartin, Lifu Chang, Eric Beisser, Frederic Brault, and Joshua Zusman, "Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns," Proc. SPIE 12495, DTCO and Computational Patterning II, 1249511 (Presented at SPIE Advanced Lithography + Patterning: March 02, 2023; Published: 28 April 2023); https://doi.org/10.1117/12.2657011.