The development of optical devices requires the patterning of non-conventional shapes on the wafers [1,2,3,4,5]. In addition to the specific challenges related to the treatment of these curvilinear patterns, an accurate proximity correction must be provided. The Critical Dimensions (CDs) of such patterns are indeed around 100nm, which requires the implementation of advanced lithography processes, similar to CMOS microelectronics technologies. In order to develop a production compliant and robust OPC solution, we previously demonstrated the need for etch bias modelling [1]. Taking the example of optical metasurfaces application, and using ASML’s Tachyon OPC+ platform, we will present the implementation of an OPC flow suitable for curvilinear patterns, starting from the metrology strategy. We will then discuss the etch model calibration methodology, model-based etch bias correction implementation in OPC, and global OPC performance.

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Elodie Sungauer, Laurent Depre, and Raphael La Greca, "Etch model calibration and usage in OPC flow for curvilinear layouts," Proc. SPIE 12495, DTCO and Computational Patterning II, 124951H (Presented at SPIE Advanced Lithography + Patterning: March 02, 2023; Published: 28 April 2023); https://doi.org/10.1117/12.2657676.