From Event: SPIE Advanced Lithography + Patterning, 2023
High integration of semiconductor processes is being made to realize high performance in miniaturized chips. The performance of a semiconductor chip may vary depending on target variables such as thickness, line width, shape, composition, and physical properties of each layer constituting the chip. Therefore, in order to secure chip performance, accurate detection of target variable values and quality control are required, and it is necessary to check in advance for defects that may occur during the process. Optical inspection technology is widely used in the semiconductor metrology field due to its advantage in that it can detect defects in the wafer at high speed by scanning the wafer with a light source having a specific wavelength band. However, in recent years, the size of defects caused by high integration and miniaturization of semiconductor chip processes is getting smaller, and thus there is a limit to detecting micro defects using conventional optical methods. In this study, we propose an algorithm to improve the defect detection performance by utilizing multi-scan images acquired under various conditions. Using the suggested algorithm, it was confirmed that the SNR (Signal to noise ratio) of the defect of interest was improved by about 99%, and the classification performance for noise was improved by 4 times.
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Sungyoon Ryu, Seunghyeok Son, Chan-Gi Jeon, Sujin Lee, Minho Rim, Yusin Yang, and Younghoon Sohn, "A study on defect signal improvement using multi-scan optic patch images and new detection algorithm," Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124960Y (Presented at SPIE Advanced Lithography + Patterning: March 01, 2023; Published: 27 April 2023); https://doi.org/10.1117/12.2657845.