Electronic circuit designers commonly start their design process with a schematic, namely an abstract representation of the physical circuit. In integrated photonics on the other hand, it is common for the design to begin at the physical component level, and create a layout by connecting components with interconnects. In this paper, we discuss how to create a schematic from the physical layout via netlist extraction, which enables circuit simulations. Post-layout extraction can also be used to predict how fabrication variability and non-uniformity will impact circuit performance. This is based on the component position information, compact models that are parameterized for dimensional variations, and manufacturing variability models such as a simulated wafer thickness map. This final step is critical in understanding how real-world silicon photonic circuits will behave. We present an example based on treating the ring resonator as a circuit. A silicon photonics design kit, as described here, is available for download at http://github.com/lukasc-ubc/SiEPIC_EBeam_PDK.
Lukas Chrostowski, Zeqin Lu, Jonas Flueckiger, Xu Wang, Jackson Klein, Amy Liu, Jaspreet Jhoja, and James Pond, "Design and simulation of silicon photonic schematics and layouts," Proc. SPIE 9891, Silicon Photonics and Photonic Integrated Circuits V, 989114 (Presented at SPIE Photonics Europe: April 06, 2016; Published: 13 May 2016); https://doi.org/10.1117/12.2230376.
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