Spin-transfer torque (STT) and spin-orbit torque (SOT) based magnetic tunnel junction (MTJ) devices are emerging as strong contenders for the next generation memories. Conventional STT magneto-resistive random access memory (MRAM) offers lower power, non-volatility and CMOS process compatibility. However, higher current requirement during the write operation leads to tunnel barrier reliability issues and larger access devices. SOT-MRAM eliminates the reliability issues with strong spin polarized current (100%) and separate read/write current paths; however, the additional two access transistors in SOT-MRAM results into increased cell area. Multilevel cell (MLC) structure paves a way to circumvent the problems related to the conventional STT/SOT based MTJ devices and provides enhanced integration density at reduced cost per bit. Conventional STT/SOT-MRAM requires a unit cell area of ~10-60 F2 and reported simulations have been based on available single-level MTJ compact models. However, till date no compact model exists that can capture the device physics of MLC-MTJ accurately. Hence, a novel compact model is proposed in this paper to capture the accurate device physics and behaviour of the MLC-MTJs. It is designed for MLCs with different MTJ configurations demonstrated so far, such as series and parallel free layer based MLC-MTJs. The proposed model is coded in Verilog-A, which is compatible with SPICE for circuit level simulations. The model is in close agreement with the experimental results exhibiting an average error of less than 15%.
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