Complementary FET (CFET) is the most promising device architecture for post-nanosheet CMOS scaling. Monolithic CFET is considered as natural evolution of nanosheet. However, its process integration is much more complex than nanosheet because of high aspect ratio patterning and vertical edge placement control due to stacked N-P nanosheet channels. In this paper, we will discuss approaches to solve these challenges for ultimate CMOS device scaling.

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Naoto Horiguchi, "Monolithic CFET patterning challenges for ultimate CMOS device scaling," Proc. SPIE PC12499, Advanced Etch Technology and Process Integration for Nanopatterning XII, PC1249901 (Presented at SPIE Advanced Lithography + Patterning: February 28, 2023; Published: 30 April 2023); https://doi.org/10.1117/12.2662840.6325346993112.