The complexities of VHSIC designs and a design methodology to support them are described. Design automation tool requirements are discussed for design specification, design verification, design analysis, circuit simulation, test pattern generation, layout, layout verification, and a multilevel database.

Hardware description languages (HDLs) are becoming the primary formal descriptive media for hardware designers. The motivation is to provide a common, unified language for communicating all aspects of hardware design. This communication provides a media for the specification and documentation of the hardware design. If this language were an industrial standard it could be the formal media for exchange of design information within and between companies. Current hardware design complexities require accurate interpretation and simulation. Hence, simulation is a natural adjunct to a hardware description language which provides the user with a model of the hardware. This paper describes a language overview for two implementations of Texas Instrument's Hardware Description Language: that which is part of the Design Utility System being produced by Texas Instruments under the VHSIC contract and that which is part of the internal Texas Instruments Integrated Circuit Design System. Limitations of these systems are discussed and recommendations for their improvement are presented.

The increasing stringency of the speed, power, and density requirements of signal processors for military systems over the past decade has contributed to a rapid reduction of the typical feature size of IC components and to the development of high-performance technologies such as CMOS/SOS and I²L. The continued evolution of semiconductor technologies to even smaller feature sizes and improved performance characteristics indicates the need to reorganize the chip architecture into cells and to provide a two-level interconnect scheme.(1-7) Specifically the first level of interconnect would be used for low-energy communication within a cell and the second level would route power around the chip and provide communication between cells. Further advantages can be gained if the first level metal is a low resistivity refractory material.(1-7)

The need for a reliable multilevel metal interconnect for high density, high performance ICs is well recognized. Successful development of a double level metal process would result in significant improvement in speed, higher device packing density, the fabrication of new structures not available using single level metallization, the reduction of cross talk between metal lines, and the fabrication of gate arrays. A double level metal (DLM) interconnect technology using aluminum or aluminum alloy for the first metal layer has yet to be widely implemented. This is mainly caused by difficulty in forming a high quality inter-level insulator. The initial success achieved with the Photo-CVD oxide process (PHOTOXTM) developed for the deposition of Si0₂ as an interlevel insulator for DLM applications is reported herein. The PHOTOX-process is a low temperature (50 to 300°C), low pressure (approximately 1 torr) technique, which is inherently free of any high energy radiation that could cause material damage. The insulator properties required for DLM processing have been exhibited routinely with the PHOTOX silicon dioxide dielectric. The inherent dielectric strength of PHOTOX Si0₂ is sufficient for it to be used as a DLM insulator. Excellent mechanical properties such as conformal coating, smooth surface morphology, low pinhole density, lack of cracking, and good adhesion to underlying surfaces are achieved. Electrical evaluation of large area capacitors, serpentine capacitors, and via chains have confirmed the quality of the oxide bulk properties. Initial life test results from temperature-cycled packaged capacitors indicate the potential for PHOTOX Si0₂ reliability.

The advent of large scale, mosaic focal planes has presented a serious challenge to sianal processing systems. The impact of VHSIC technology on the design of these systems is analyzed in light of experience on several programs. When VHSIC technology is applied, the architectures generally take the form of a high speed, VHSIC, pipeline signal processor followed by a data processor constructed of VHSIC general purpose computers. The increased speed and canability of the VHSIC aeneral purpose computers allows them to be moved forward in the architecture, much closer to the focal plane. VHSIC technology shrinks the logic components of the systems and leads to systems that are very memory intensive. The system impact of these memory intensive designs is analyzed. If VHSIC architectures are operated in space, they are susceptible to single event errors due to cosmic radiation. The impact of these errors on both logic and memory is discussed.

Advanced integrated circuits when exposed to a space environment are prone to single event radiation effects. Accelerators can provide particle beams which test electrical components in a simulation of the space environments. Methods are available in most cases to relate the accelerator results to predicted performance in space.

Criteria and procedures that provide assurance as to a manufacturer's ability to provide functionally reproducible and reliable devices are desirable prior to user commitment to the design of a custom device. Additions and modifications to current practices are necessary when procurement of small batches of high-density, custom microelectronic devices are anticipated. This paper analyzes the problems that may be encountered with emerging VLSI/VHSIC technologies and describes a method that, if implemented, could minimize costs and adverse schedule impact to the user.

Computational requirements for proposed satellite surveillance missions have grown beyond the capabilities of existing space qualified computers. In fact, throughput for a space processor of the future is expected to be in excess of 50 million instructions per second (MIPS). This processing capability must be attained with minimum system size, weight and power. Recent studies indicate that a distributed processing system is a realistic method of attaining this goal. Complementary metal oxide semiconductor (CMOS) and very high speed integrated circuits (VHSIC) technologies were evaluated for the design of a modular, high throughput, space computer. Operational and physical property attributes considered include: 1) processing throughput versus system power, 2) local heat dissipation, 3) device radiation tolerance and 4) multiprocessor communication techniques. The conclusion of the evaluation makes a series of recommendations and suggests a set of tests to enable the space community to select the optimum technology and system architecture for a modular space processing system.

The RF portion of a navigation/communication system is the most costly section to manufacture due to the extensive use of discrete circuitry, critical alignment of components, and the combersome packaging techniques required. In order to reduce cost, size and power consumption, circuit integration is necessary. The extremely high gain-bandwidth requirements however, place the RF section beyond the reach of conventional silicon monolithic LSI implementation or microprocessor techniques. In this paper, we report the development of an RF LSI monolithic GaAs technology which promises to reduce the RF receiver functions to a 3 to 4 chip set. Test chips have been developed that contain both analog and digital functions operating at UHF and L-band frequencies. These circuits represent the critical building blocks for many satellite navigation and communication systems. Test results indicate operation up to 1.6 GHz. Detailed circuit design and circuit performance will be discussed.

Simulation provides a valuable tool for resolving design decisions in the areas of system development and evaluation. Our experience is based on using simulation to verify and validate large complex systems supporting the U.S. Air Force launch vehicle programs. The complexities of systems built of Very High Speed Integrated Circuits (VHSIC) indicate that simulation will be needed to support many aspects of the VHSIC program design and development. This paper provides insight into simulation and its possible use as a design tool in connection with the VHSIC program. Specifically, simulation should be used to guide and control design decisions.

The combined requirements of size, weight, throughput, reliability, and testability imposed on signal and data processing systems by new electro-optical sensors cannot be met with conventional architectures or circuit technology. One solution to this problem is described in this paper. This solution is a result of five years of work done to date on the Modular Missile Borne Computer (MMBC) combined with the more recent Very High Speed Integrated Circuit (VHSIC) program.

Control Data has an established reputation as designer and manufacturer of military general-purpose (GP) embedded computers. This afternoon we are going to address some of the challenges and trade-offs related to VHSIC and the GP computer arena. Specifically there are four challenges that I will address today.

The VHSIC Vector Arithmetic Logic Unit (VALU) is a particularly powerful computational resource which has been optimized for signal and image processing. The device features a sixteen bit parallel multiplier, a sixteen bit full capability ALU, a thirty-six bit adder/subtractor, sixteen words of multi-port register file, and a user specified 96K Read Only Memory for storage of sixty-two bit microinstructions. The versatility of the VALU architecture and its associated support devices permit the construction of various image processing configurations including: single VALU array processors, arrays of array processors, and systolic array structures for extremely high speed image processing requirements. The different image processor architectural configurations are reviewed and examples of specific algorithm executions are given to demonstrate the applicability of each approach when related to algorithm partitioning, throughput requirements, flexibility requirements, size requirements, and power requirements.

An application of Very High Speed Integrated Circuit (VHSIC) technology to military electro-optical system design is described. In detail are the influences of real-time image processing requirements and the evolution of algorithms for target detection and classification on an image signal processing architecture. In addition a potential implementation is demostrated of an Image Analysis Chip providing both high throughput and flexibility to perform many of the front-end signal processing functions required for target acquisition, fire control, and guidance systems.

In this paper we discuss a common set of image processing functions arising from selected Army, Air Force, and Navy tactical scenarios. These include target detection, recognition, multiple target tracking, target handoff, fire control, bandwidth compression and aimpoint selection. A number of VHSIC objectives are considered, including reduced acquisition cost, fault tolerance, reliability, maintainability, reduced support costs, and reduced pilot load. The image processing problem requires a throughput capacity of 10x10⁹ instructions/sec in a volume of less than one cubic foot and a power requirement of less than 300 watts. Approaches to the design problem in terms of architecture, software, hardware, and testability are indicated.

The recent availability of high-performance infrared imaging systems of different types and designs has revealed certain difficulties in correlating practical "field-test" performance with the widely used "MRTD" (minimum resolvable temperature difference) values in the form developed during the early period of the IR imaging activities since 1955. This applies in particular also to systems using mosaic array detectors of both the "scanning" and the "staring" types. Such difficulties may be satisfactorily surmounted by uncoupling "sensitivity" and "resolution" performance parameters. The basic theory will be presented together with practical examples for representative systems and comparison with "MRTD" curves, which remain useful for noise-level characterisation. The imaging performance analysis is necessary also for an assessment of adequate sensitivity and resolution in a variety of pattern-recognition applications and of computer-speed requirements in the use of IR "smart sensor" systems. A basic theoretical analysis (to be introduced) shows that VSHIC computer systems (with computational speeds at least some loo times greater than from presently available computers) would be required for representative real-time use of IR sensors in the most demanding applications.