This PDF file contains the front matter associated with SPIE Proceedings Volume 11908, including the Title Page, Copyright information, and Table of Contents.

The world is rapidly shifting towards data-centric computing model with significant growth in compute, storage and networking. Moore’s law scaling to reduce power, improve performance and reduce area and cost per transistor to support data centric growth places significant challenges for photomask process, control, and metrology. DUV lithography continues to be workhorse technology and continues to drive innovation. Multiple solutions are being developed to solve DUV mask challenges associated with a big die requirement. While DUV production is being projected to be strong for next few years, EUV is picking up pace and being deployed in high volume manufacturing. EUV is an opportunity-rich environment for improvements and innovations that will continue to advance the journey. EUV HiNA is a major step in the lithography paradigm where 0.55 NA EUV optics will enable a shift to sub-10nm resolution. The HiNA mask ecosystem will adapt by growing the newly created low NA EUV supply chain into new directions. The photomask environment will continue to bring creativity, drive innovations and gain commercial rewards.

Progress is aggressively being made to advance nanomachining photomask repair technology to the next level of performance. This next level would allow for the dimensional modification of surfaces using diamond AFM tips (NanoBits) with nominal aspect ratios (AR’s) greater than or equal to 1.3 (including 1.8) in the smallest features in production. Prior work along these lines will be presented with new results from a novel process with comparison to established nanomachining processes. These results will evaluate test repairs on the most advanced photomasks currently in production including OMOG and EUV.

Mask process correction (MPC) played a key part improving yield in 14 nm technology node and below using deep ultraviolet lithography (DUVL). Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7 nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern layers at aggressive pitch using a single exposure. Mask critical dimension targeting was found to be a critical factor for yielding wafer process, MPC will be necessary to correct for mask process errors. This paper will focus on building MPC models for EUV mask processes exposed on a variable shape beam lithography tool.

Sub-nanometer accuracy attainable with electron micrograph SEM images is the only way to “see” well enough for the mask analysis needed in EUV mask production. Because SEM images are pixel dose maps, deep learning (DL) offers an attractive alternative to the tedious and error-prone mask analysis performed by the operators and expert field application engineers in today’s mask shops. However, production demands preclude collecting a large enough variety and number of real SEM images to effectively train deep learning models. We have found that digital twins that can mimic the SEM images derived from CAD data provide an exceptional way to synthesize ample data to train effective DL models. Previous studies [1, 2, 3, 4] have shown how deep learning can be used to create digital twins. However, it was unclear if SEM images generated with digital twins would have sufficient quality to train a deep learning network to classify real SEM images. This paper shows how we built three DL tools for SEM-based mask analysis. The first tool automatically filters good quality SEM images, particularly for test chips, using a DL-based binary classifier. A second tool uses another DL model to align CAD and SEM images for applications where it is important that features on both the images are properly aligned. A third tool uses a DL multi-class classifier to categorize various types of VSB mask writer defects. In developing the three tools, we trained state-of-the-art deep neural networks on SEM images generated using digital twins to achieve accurate results on real SEM images. Furthermore, we validated the results of trained deep learning models through model visualization and accuracy-metric evaluation.

MPC has been a technology enabler since 32nm technology node, and the number of mask layers receiving MPC increases as technology node advances. Model-based Mask Process Correction (MB-MPC) has evolved from correction based on short-range Gaussian to full Machine Learning (ML) based model and correction. Model-based MPC has demonstrated efficacy in reducing mask error on advanced nodes, but often requires extensive computing resource to achieve the stringent mask fidelity and Critical Dimension (CD) requirements. On the other hand, rule-based Mask Process Correction (RB-MPC) has the advantage of fast turn-around time. This paper presents an approach to rule-based MPC that seeks to extract the maximum benefits of model-based MPC. The rules cover critical geometrical ‘building blocks’ such as lines, contacts, line-ends, notches. Derivation of the rules is guided by a mask process model. The goal of RB-MPC is to mitigate the long runtime of MB-MPC while minimizing loss in patterning fidelity. We will describe the methodology of rule derivation, implementation, and verification of RB-MPC. The RB-MPC approach meets accuracy requirements for 32-22nm technology nodes. For more advanced technology nodes, a hybrid RB-MB-MPC recipe is proposed to achieve both high accuracy and fast runtime.

Since 2019, EUV lithography has started to be used for the mass production of 7-nm-node-logic devices. However, many significant issues on EUV lithography still remain in the fabrication of future devices. The technical issues are the development technologies of resist, mask, and EUV light source. Therefore, many significant fundamental researches have been carried out at our facility. Here the EUV mask technologies is highlighted. It is described the fundamental research activities on EUV lithography at NewSUBARU synchrotron light facility, which is related with EUV mask technologies.

Stereophonic lithography applying a magic-mirror optics composed of faced parabolic mirrors is proposed. In the magic mirror system, a real image of an object placed on the base of the lower mirror is formed at the aperture center of upper mirror as if an actual object is floating in the air. The image is formed by illuminating the object by the downward light supplied through the upper mirror aperture. In the new optics originated in this research, a lower mirror with an aperture similar to the upper mirror is used, and the object held at the center of the lower mirror aperture is illuminated obliquely by the upward light supplied through the lower mirror aperture. At first, using reflective objects, image formations were demonstrated. When an object was placed at various height of the optical axis, an image almost similar to the object was projected successfully in a wide height range of the object. The size and the height position of the image were almost regularly changed according to the axial height shift of the object. However, image contrasts sufficiently high for the lithographic patterning were not obtained. For this reason, transparent objects were tried next, and the illumination light was adjusted as most of the light rays hit the middle parts of the upper mirror surface. As a result, considerably high-contrast images were formed. Although some distortions were observed in image shapes, feasibility of the new stereophonic projection system was confirmed. The new technology is prospective.

Automatic design systems of the Built-in Lens Mask (BILM) for three-dimensional photo lithography will be presented based on conventional feedback control procedure. The 3Dstructure, which is imaged by BILM sometimes missing the pattern due to optical interferences. By optimization of the BILM mask, the optical image becomes fine, smooth and unity.

ArF lithography is still applied to the majority of critical layers, even with increasing of extreme ultraviolet lithography in leading-edge production. As wafer design shrinks, conventional 6% phase shift mask (PSM) becomes hard to meet the ArF lithography requirements especially for array dot on mask (hole on wafer). Therefore, transmission dependency was evaluated by mask 3D simulation, and it was found that 30% transmission has the best lithographic performances for array dot. Based on these results, mask blank and mask making process for new 30% PSM were developed. Wafer printability test using negative tone development demonstrated that new 30% PSM has better process window and mask error enhancement factor (MEEF) than conventional 6% PSM for array dot (hole on wafer). To investigate further application of new 30% PSM, lithography performances of various patterns were evaluated by mask 3D simulation and aerial image measurement system (AIMSTM). The results indicated that new 30% PSM has larger lithography margin than 6% PSM for iso dot, iso line and logic pattern. Additionally, wafer printability test demonstrated that new 30% PSM has better process window than 6% PSM for iso dot. Defect control is also an important factor in high volume manufacturing. Therefore, it is necessary to evaluate the repairability and printability of the defects on new 30% PSM. We repaired various types of defects by electron-beam repair tool and confirmed the repairability by AIMS. And the defect printability of new 30% PSM and 6% PSM to critical dimension (CD) on wafer was evaluated by program defect mask that has pin dot, extrusion and intrusion defects.

Since the mid-2010s, mobile organic light emitting diode (OLED) panels have increased the demand for increased resolution in Flat Panel Display (FPD) photomasks [1]. In response to this demand, a 1.5 um Line and Space target exposure system for 800ppi OLED panels ware released in the mid-2010s. In addition, exposure system manufacturers are developing 1.2um Line and Space target exposure systems to produce ultra-high-definition OLEDs in the 800-1000ppi range [2]. While photomask manufacturers are required to have defect assurance capabilities for the next generation design, there is no standard industry roadmap in the field of FPD lithography. We believe that what is really necessary for the OLED panels manufacturer is to ensure that the pattern on the photomask is transferred to the OLED panel without any problems. Instead of the assurance based on the size of the defect on the photomask, we propose a new type of photomask assurance, which is the assurance for the pattern transfer to the OLED panel by the photomask maker. In this report, we will report on our new type FPD photomask assurance proposal.

The eBeam Initiative has conducted an annual survey of industry luminaries for the past nine years to gather predictions of industry trends. The Luminaries survey was completed in July 2020. At the same time, the eBeam Initiative completed its sixth annual Mask Makers survey with anonymous feedback from 10 captive and merchant photomask manufacturers. Taken together, the surveys in 2020 reflected that the semiconductor mask-making industry is going through transitions on multiple fronts at the same time yet are upbeat about the photomask market outlook.

Nanoimprint lithography (NIL) is a promising technology on next generation lithography for the fabrication of semiconductor devices. NIL is a one-to-one lithographic technology with a contact transfer methodology using templates. Therefore, critical dimension (CD) error and defect performance of templates has direct impact on wafer performance. The previous paper reported that the self-aligned double patterning (SADP) process on master template had better performance on resolution and defect performance [2]. In proceeding with development of SADP template process technology, we found that CD errors occurred in the area with a pattern density change. CD control over any pattern density is one of the critical issues. In this report, we have investigated the impact of the proximity effect correction (PEC) and fogging effect correction (FEC) parameters for electron beam writing on gap space and core space. It was found that the optimal PEC parameter for resist CD is not the best for the core space and the gap space. The resist CD is uniform, but there is a difference in resist shape on the local pattern density variation. It was also found that the core space had dependency on global pattern density even if the optimal FEC parameter for resist CD was applied. FEC can correct resist CD, but it cannot adjust resist shape. By using the optimal PEC and FEC parameters for SADP process, the gap space range of 0.6 nm and the core space range of 0.5 nm were successfully obtained.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Computational technologies are still in the course of development for NIL. Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their daily toolbox. The most challenging issue in NIL process simulation is the scale difference of each component of the system. The template pattern depth and the residual resist film thickness are generally of the order of a few tens of nanometers, while the process needs to work over the entire shot size, which is typically of the order of 10 mm square. This amounts to a scale difference of the order of 106. Therefore, in order to calculate the nanoimprint process with conventional fluid structure interaction (FSI) simulators, an enormous number of meshes is required, which results in computation times that are unacceptable. In this paper, we introduce a new process simulator which directly inputs the process parameters, simulates the whole imprinting process, and evaluates the quality of the resulting resist film. To overcome the scale differences, our simulator utilizes analytically integrated expressions which reduce the dimensions of the calculation region. In addition, the simulator can independently consider the positions of the droplets and calculate the droplet coalescence, thereby predicting the distribution of the non-fill areas which originate from the trapped gas between the droplets. The simulator has been applied to the actual NIL system and some examples of its applications are presented in this work.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL and attractive solution. The purpose of this paper is to review the performance improvements related to overlay and introduce edge placement error analysis for NIL. Improvements in overlay include an extension in the range for high order distortion correction and improvements in control methods such as imprint force, mask to wafer tip/tilt and wafer zone pneumatics near the wafer edge. We also introduce the pattern transfer scheme used to etch features with half pitches below 20nm.

Extreme ultraviolet (EUV) pellicle has been widely used to control the defectivity of EUV mask out of airborne debris. The EUV mask equipped with pellicle is typically stored within a EUV inner pod (EIP) until use. However, such pellicle is easily deformed due to its structural weakness, the risk of thermal stress and so on, thereby altering its transmission as well as impacting the yield of EUV fabrication. Since the activity of EUV pellicle alone is comprehensively studied, the exploration of pellicle mechanical stress within EIP is relatively less addressed. Here, we present an emerging approach via a chromatic confocal sensor to investigate the above issue. The chromatic sensor was utilized to detect the surface of pellicle based on the reflected light wavelength with a 22 nm axial resolution. A conductance tester was utilized to simulate the pump and vent characteristics, according to ASML and core EUV scanners. During the pump/vent cycle (from atmospheric pressure to 5 Pa and vice versa), the EUV pellicle was deflected from -400 μm to 200 μm. We further analyzed the stress of deformed pellicle by both numerical simulation and theoretical calculation. Interestingly, the graphene-mediated pellicle revealed a more stiffer activity than other material-based pellicles (such as poly-silicon, SiC and Si3N4) under a range of pressure difference (0 to 10 Pa). Taken together, the proposed approach has been successfully demonstrated to enable real-time examination of EUV pellicle activity within EIP, which should be capable for worldwide EUV mask cores.

EUV lithography enters the high-volume manufacturing stage, and the semiconductor industry considers a lithography-wavelength- matched actinic patterned mask inspection (APMI) tool to be a crucial infrastructure for EUV mask qualification. ACTIS^TM, the world’s first high-sensitivity actinic patterned mask inspection system, was released in 2019. ACTIS detects lithographic impact defects that cannot be seen with the existing DUV inspection tools. The actual results of production mask inspection show that only an actinic EUV inspection system can visualize small surface topography and phase changes that propagate through multilayer stacks. In this paper, we present the progress of ACTIS inspection technology, defect sensitivity, die-to-database inspection and through pellicle inspection. For technology nodes beyond N3, a high-NA EUV anamorphic lithography system will be used. The mask structure in the high-NA era will be different from the current configuration. For inspection tool design, it is necessary to adopt a different magnification of mask-to-wafer projection in the vertical and horizontal directions. ACTIS has the extendibility to a high-NA system since its projection NA area has room for extension in one direction. The high-NA EUV inspection tool will be discussed in this paper as well.

The Laser-assisted discharge-produced (LDP) plasma EUV source was developed as a light source for actinic mask inspection and beamline application. Since the focused laser irradiation is used to ignite the discharge, the LDP plasma has a unique feature of high brightness and high power. It can be operated at the frequency of up to 10 kHz generating <200 W/mm2/sr in-band EUV brightness at plasma. The source reliability is also proven in the field as a source for actinic mask inspection. In the paper, the key performances of the LDP source will be discussed.

High volume manufacturing of semiconductors using extreme ultraviolet lithography (EUVL) is off to a good start, and development of high-NA EUVL tool has started; however, EUV mask pattern inspection, one key technology supporting EUVL, is still not ready in terms of fully satisfying customers' major requirements, such as 1) defect sensitivity, 2) throughput, and 3) cost of ownership (CoO). There are three tool candidates that have the potential of meeting these requirements: optical inspection, actinic inspection, and e-beam inspection. The resolution of the optical inspection tool has almost reached its limit. The actinic inspection tool satisfies both defect sensitivity and throughput requirements, but the cost is high and it needs to support D2DB inspection capability. The e-beam tool has high resolution and sensitivity, but its low throughput which is a key issue. With this background, NuFlare has optimized its multi e-beam optics system to inspect EUV masks, and has made progress in verifying a POC tool as well as develop new image processing technology. From these verifications, the development has moved on to the feasibility study of inspecting EUV mask pattern defects with D2D and D2DB for the 5nm node and beyond. In this paper, we will present our technology for EUV mask inspection as well as our latest results.

In this paper, we present results of long-term stability tests of a low-loss (<0.55 dB) hollow core fiber (HCF) to standard optical fiber interconnection prepared by modified gluing-based fiber-array technology. We measured insertion loss of three interconnected HCF samples over a period of 100 days at room temperature, observing a variation in insertion loss of less than 0.02 dB. Subsequently, we placed the HCF samples in a climatic chamber and heated to +85◦C in four cycles. Maximum insertion loss variation of 0.10 dB was observed for HCF samples with angled 8◦ interconnections and only 0.02 dB for a HCF sample with a flat interconnection.

A multi-beam mask writer, MBM-2000 is developed for the N3 semiconductor production. It is designed to accomplish high throughput with 16-nm beam and large current density 2.5 A/cm2. It is equipped with curve data format MBF2.0 to allow writing of small curve patterns in EUV masks and curvilinear OPC patterns in optical masks. To improve patterning resolution, pixel-level dose correction (PLDC) is implemented which corrects and enhances profile of dose deposited in resist. Writing tests have proven the global position accuracy that meets MBM-2000’s specification and the effectiveness of fidelity improvement function of PLDC.

To this day there is no established practical method available to identify the “optimal” base dose in e-Beam lithography for mask making. Methods range from choosing the “zero-bias” exposure dose that yields CDmeasured = CDtarget to real isofocal calibrations that require to print the structures at different blurs/focus settings. While the latter yields an optimal base dose, it requires a significant experimental procedure, whereas the former uses a pretty simple experiment but will likely yield a non-optimal base dose due to process effects (e.g., lateral resist development). Here we present a novel method to find the optimum base dose for e-Beam mask exposures that requires only a simple experiment. Surprisingly, the exposure doses required to print features with different densities at the same CD does depend on the process point, adding an error term to the proximity effect correction in case the correction is not aligned to this. This is due to the fact that for a given stack and acceleration voltage, a PEC method will deliver one fixed dose range, whereas the experimentally required dose range depends on the process point chosen. This observation can be used to calibrate the base dose such that it matches the dose range obtained from PEC. Moreover, it can be used to add a new criterion to proximity effect correction – the iso-focal condition - to not only correct for line width (also called critical dimension, CD) linearity and density dependent effect, but to also add immunity to process variations such as focus and blur variations.

Narrowed CD specifications coupled with very tight cycle time requirements have resulted in search for improvement opportunities in CD stability and tuning options for mask fabrication unit processes, including pattern generation, resist development and etch, which may yield narrower scattering band of CD off-target (CDO) of final products. Targeting models are already in productive use at AMTC, accounting for different mask and blank types, clear field, resist type, pattern type and many other parameters. This targeting model is static however, and changes in the CD performance of contributing factors must be adjusted manually when CD drift inevitably occurs. In the past, several approaches to introduce time-based corrections were pursued. Correction of step function of the resulting CDO caused by e.g. resist lot change is the easier task, due to the fact that such factors can be closely analyzed prior to productive use by test, and offset accounting for the individual factor can be introduced. More troubles cause factors, whose effects on CDO is smooth and can be observed as long-term drift in the CDO. The CD drift is frequently of very different origin and effects of several factors are overlapping in time. By measuring the final CD on the products, we can see only the ‘envelope’ of all the effects. To target such factors, we need to identify their root cause and ideally an easy-to-monitor indicator. In this paper we show an analysis approach to identify the most significant and vital indicators to process bias. Analysis of production data covering several manufacturing steps including metrology over more than three years was performed. Using machine learning methods, a “big data” set is reduced, and the most appropriate model is selected using statistical methods. Criteria for selection of factors were significance level in analysis of variance and the distribution of residuals was used for model comparison. Based on these factors a model of the etch contribution to the CD was established, describing the variation of the etch process for a virtual mask with constant clear field, resist sensitivity and absorber composition and thickness. This model is based on the process data collected at the etch process during processing of each mask processed with the same recipe. Monitoring this time trend of the “modelled etch bias” gives very fast feedback about the stability of the etch process and evolution of the etch contribution to CD. This data is used to trigger appropriate corrective actions to further stabilize the manufacturing process.

In prior work, progress was shown in the systematic characterization of the process space for efficient and effective repair of extreme ultraviolet (EUV) photomasks using an ultrafast (femtosecond) pulsed deep ultraviolet (DUV) laser apparatus. In this work, the full analysis and conclusions, along with any additional test results are shown. This includes an analysis of the impact of laser repair on the phase shift of the multilayer using multiple processes.

We evaluated the charge-separated spectra of highly charged suprathermal gadolinium (Gd) ions from a 1064-nm, nanosecond laser-produced plasma (LPP) extreme ultraviolet (EUV) source developed for beyond EUV (BEUV) lithography. The charge distribution of these suprathermal ions emitted from a solid planar Gd target was measured by an electrostatic energy analyzer (ESA). The maximum ionic charge state was observed to be Z = 16 and to possess a maximum energy of about 15 keV at the optimum laser intensity of 2 x 10¹² W/cm2 to produce the efficient 6.7-nm EUV emission. This evaluation provides important information essential for the development of debris mitigation schemes in the BEUV source for next generation lithography.

We demonstrate a supercontinuum vector beam analysis based on interactions between angular-variant polarization and birefringence in the solid state. The supercontinuum vector beam analysis provides both the two-dimensional distribution of the birefringence and the wavelength properties, from a single-shot image. The angular resolutions of the retardance and azimuthal angle are evaluated. The retardances were determined at 650 nm to be 92.9° ± 9.3° and 87.1° ± 18.7°, respectively. The spatial resolution of 60 μm and the resolution of the retardance was 12 mrad.

We introduce a new algorithm (DFM Via Shift) to reposition vertical interconnect access (VIA) design patterns, considering the retargeted metal (both upper and lower layer) pattern, the user-defined max-shifting range, and the VIA design rule, for the purpose of achieving maximum metal coverage of VIAs. The DFM Via Shift algorithm considers VIAs that interact with each other based on spacing rules as a VIA cluster. All VIAs in a cluster are co-optimized, allowing for fully-covered VIAs with good positioning to be shifted to allow other, more critical VIAs to be optimized in some scenarios. We present the results of our research showing that the overall metal coverage of VIAs in 25nm node test chips can be significantly improved with repositioning. Nearly 95% of VIAs exposed out of metal after retargeting can be optimized to new, fully-covered positions in one of the test cases of the advanced node.

An extreme ultraviolet (EUV) light with a wavelength of 13.5 nm has been introduced to 7 nm FinFET technology. Optical elements such as Mo/Si multilayer mirror in lithography equipment are contaminated with hydrocarbon during the EUV light irradiation. The reflectance of the mirrors is decreased by carbon contamination. Therefore, the removal method of the carbon contamination is required for reduction of maintenance cost. The surface treatment using atomic hydrogen generated by a heated tungsten mesh, called as atomic hydrogen annealing (AHA), have been investigated for cleaning of the optical elements used in the synchrotron facility. The Au/Cr/Si substrate, Ni mirror and Ni diffraction grating with carbon contamination were cleaned and the reflectance of the mirrors was recovered by AHA. In addition, the AHA conditions could be optimized for cleaning of Mo/Si multilayer mirrors from the relationship between the treatment conditions and degradation. Furthermore, to clarify the reaction of atomic hydrogen with not only C-C bond but also C-O bond, the graphene oxide (GO) film was also treated by AHA. The C-O-C bonds in the GO films were preferentially reduced by AHA. It is found that the surface contamination consisting of hydrocarbon and/or C-O bond on the optical elements is removed without damage. The ability of atomic hydrogen to clean the optical elements had been confirmed. The findings are useful for the advanced lithography technology using EUV light.

In 2019, EUV lithography technology with a wavelength of 13.5 nm was used for the mass production of semiconductor logic devices with 7 nm node. As with small feature size of electronic circuits in semiconductor device will be required in the future, beyond EUV (BEUV) lithography with exposure wavelength around 6.7 nm is a candidate for the next generation lithography. In BEUV, the developments of high-reflective multilayers, high-sensitive resists, and high-power light sources are critical issues. Thus, we have developed BEUV evaluation tools in NewSUBARU synchrotron light facility. Accurate BEUV reflectometry is significant for the development of high-reflective BEUV multilayer. For the accurate reflectometry, higher-diffraction-order generated from a monochromator should be suppressed. At the BL10 beamline at NewSUBARU, the components of second and third-diffraction-order light are 7% mixed into the BEUV measurement light. Mo transmission filter with a 200-nm-thick was previously used to suppress the higher-order light to 1/10, which was insufficient for target accuracy of 0.1%. We have developed a high-order-light cutting unit consisting of two mirrors with TiO₂ coating, which suppressed the high-order light to 1/100.

At EUV lithography, an EUV mirror can be easily contaminated with carbon. This carbon contamination causes the reflectance drop of the Mo/Si multilayer mirror. For the carbon-contamination cleaning, hydrogen gas is introduced at a pressure of a few Pascal in the EUV exposure tool. However, during this process, the hydrogen damage would be caused on a Mo/Si multilayer, which would decrease EUV reflectance of the multilayer. The cleaning rate and damage threshold of hydrogen pressure and EUV dose were not well known. Therefore, an EUV irradiation tool in hydrogen atmosphere is developed and installed at the BL09 beamline of the NewSUBARU synchrotron light facility to evaluate the irradiation durability and cleaning effect of the Mo/Si multilayer under these conditions. The EUV-irradiation intensity was up to 6 W/cm², and hydrogen pressure was up to 70 Pa. The contamination was occurred at the low-hydrogen-pressure conditions from 0 to 5 Pa. The contamination was not occurred at the high-hydrogen-pressure condition of 20 and 68 Pa. In addition, the sample with many particles on the surface was damaged by the EUV-induced plasma.

In modern advanced IC fabs, reticle management is essential for process control and yield management, since any reticle issue can potentially impact thousands of wafers, resulting in a huge economic loss. For reticle caused issues, the possibility of human mistakes made in defect disposition has dramatically increased as the defects on reticles become more complicated. The difficulty in defect disposition originates from smaller critical dimension (CD) and complex pattern designs like aggressive OPC and SRAF. Conventionally, defect disposition after reticle inspection is done by operators or engineers, and defects are evaluated based on engineers’ experience or AIMS tool, which are high risk and time-consuming methods. Use of automated defect disposition solutions has been reported in some photomask shops, but in DRAM fabs, an efficient and accurate defect disposition system is not yet present. In collaboration with KLA, Changxin Memory Technology (CXMT) accessed and utilized KLA’s Reticle Analyzer (RA), an intuitive web-based analysis interface that integrates Automatic Defect Classification (ADC), Lithographic Printability Review (LPR), and Defect Progress Monitor (DPM) to overcome reticle defect disposition difficulties. The comprehensive analytics tool systematically disposes all defects detected by KLA reticle inspection systems, eliminating human error in defect classification and providing 99.5% accuracy without under-classifying any defects. Furthermore, CXMT studied the LPR solution for multiple critical layers with programmed-defect masks, then verified the simulated LPR results in CD error (CDE). The correlation between LPR results and wafer printing results shows accurate CDE prediction in high volume production. Additionally, DPM was used to generate statistical process control like charts for reticle defectivity. This study shows that the integrated RA software offers a modern solution for wafer fabs that automates reticle defect management and shortens time to decision for engineers.

Fine particles (less than 5 micrometers in diameter) do not affect most industrial processes, but they can have a disastrous impact on semiconductor manufacturing. From the earliest days, manufacturing facilities have deployed air filtering and recirculation to remove particles from the cleanroom, but particles may still be generated inside process tools, where they can cause defects and yield loss. Quickly identifying when and where airborne particles originate can be challenging, but it is critical to success. Conventional methods for monitoring and diagnosing contamination problems take considerable time to return results, and, because of their intermittent nature, they may not see contamination episodes until the damage is detected by downstream inspections. In-line particle sensing (IPS) provides continuous, real-time monitoring, shortening response times and potentially limiting damage to work-in-progress.