This PDF file contains the front matter associated with SPIE Proceedings Volume 12293, including the Title Page, Copyright information, Table of Contents, and Conference Committee listings.

The demand for EUV mask qualification by inspection and metrology techniques continues with the technology node shrink. Smaller node products contain a higher number of masks that require EUV exposure. Semiconductor industries have developed a variety of inspection and metrology tools to accommodate these needs. The progress of these techniques provides well-qualified semiconductor devices. Blank manufacturing is the initial step of the mask-making process. Nanometer-scale bumps and pits on the substrate, uniformity of multilayer stack, and particle-induced wafer printing defects must be controlled during the blank-making process. Both optical mask inspection and actinic blank inspection (ABI) are widely used as effective qualification methods to detect a defect of interest. Patterned mask inspection is an essential process step for mask making. The optical pattern inspection operating at DUV wavelengths near 193nm, Actinic Patterned Mask Inspection (APMI) that uses EUV 13.5nm wavelength, and EB inspection are the presently used patterned mask inspection technologies. APMI plays a key role in EUV mask inspection due to its high-resolution imaging. The introduction of reliable database mode inspection capability added more usability for the latest single die configuration masks. To manage all the printing defects, actinic solutions have the capability to realize fast and reliable results. EUV pellicles are already in use with EUV masks. Thus, the actinic solution is considered a required inspection method for patterned mask qualification for pellicle mounted mask too. Multiple APMI systems have already been installed in mask industries for through-pellicle inspection purposes. We will report the current progress of patterned mask inspection technologies, applications, and the future roadmap for high NA EUV.

The EUV (Extreme Ultraviolet) lithography is certainly technology for 10nm or less which was used to mass-produce chips contributes to improving the minimum feature size, reducing the process step by enabling DPT (Double Patterning Technology)-less, and improving Fab. operation. Due to the expansion of EUV layers in mass production of below 5nm, EUV mask layers are continuously increasing for mass product. In order to EUV mask mass product, it is important to investment of very high expensive EUV tools and facilities, improve longterm TAT (Turn Around Time), and management of challenge yields. Among the manager of stable yields which are performed just after every process to minimize the continuous defect of mask during the process handling, take an inspection every single mask is the best way. However, investment in inspection tools and increase in inspection step are not efficient due to inefficient factory operation due to very high cost and long TAT delay. Currently most mask manufacturing companies are using manual visual inspection by human eyes and microscope. In this paper, quality monitoring system was developed to detect micro-unit front and back defects, scratches, contaminations, and coating defects by applying the Image Segmentation technique to photos taken on the front and back of the mask by modern load port (refer to wafer EFEM: End Front Equipment Module). In an effort to understand further, the authors evaluated three image segmentations technologies using CNN (Convolutional Neural Network), Sobel Edge Detector, AI (Artificial Intelligence) for mask yield managing program. This method can provide the means for determining scraps and analyzing complex log files for a quality issue found in mask fabrication. These challenges will make a paradigm shift in mask industry for the EUV mask mass product to make chips. The mask tool manufacturers unify load port specifications, it will be able to contribute to new technology and process improvement in the future.

Photomask technological innovation has entered a new renaissance at the cutting edge due to the transition from 193 nm to extreme ultraviolet (EUV) in high volume production. EUV has allowed the manufacture of smaller and smaller features on the mask with more complex multilayer material stacks that allow for little dimensional error in both patterning and defect repair. To meet these, and other challenges, work has continued to develop material independent AFM nanomachining processes that enable next-generation tips with increasing aspect ratios. Repair results from the current best of breed process, a novel and advanced nanomachining technique, will be analyzed on the latest platforms for production. Data will be reviewed to show the process capability for single pass repair on EUV patterns using 1.8 aspect ratio (AR) NanoBits® while also looking forward to implementation to higher AR NanoBits. The process will be evaluated for dimensional control to target, cleanliness, tip wear, and throughput in defect repair in single-digit nanometer technology node patterns.

With the progression of deep learning algorithms in computer vision, a lot of research is taking place in the semiconductor industry towards improving real-time defect detection and classification analysis. An Automated Defect Classification and Detection (ADCD) framework not only enables rapid measurement of dimensions and classification of defects, but also helps minimize production costs, engineering time as well as tool cycle time associated with the defect inspection process. As we continue to shrink the pitch (below 36nm), defect characterization at wafer scale becomes a key issue as it demands rapid measurement but without losing accuracy and repeatability. Also, in the context of high NA lithography (thin resist), accurate metrology becomes difficult with very noisy as well as low contrast images (No BKM exists till now). Human eyes generally demonstrate close to the Bayesian Error limit in detecting smaller objects (for example, extracting contextual information instantaneously from nanoscale defects in SEM images). However, for most One-stage and Two-stage object detectors, this is still a very challenging task due to variable image resolution and SEM (scanning electron microscope) image quality (low SNR). In this research work, we have experimented with different modified YOLOv5 object detectors to improve challenging stochastic defect detection precision. In this work, we have proposed an ensemble strategy by empirically combining multiple custom-trained models (YOLOv5n, YOLOv5s, YOLOv5m, YOLOv5l, and YOLOv5x) together at the test and inference time. We have noticed four YOLOv5 architecture variants are outperforming against our previous Ensemble ResNets model with improvements of the average precision metric (AP) of the most difficult defect classes as p gap and microbridges as well as overall mAP accuracy. With Ensemble YOLOv5, the p gap AP and microbridge AP metrices have been improved by 35% and 25.33%, respectively, whereas the overall mAP has been improved by 6.25%. The proposed Automated Defect Classification and Detection (ADCD) framework can also be used for high resolution and high-speed metrology, providing rapid identification of defects with improved certainty and further root cause investigation.

SRAF plays a critical role in mask synthesis. It is a fundamental component of masks, for Manhattan or curvilinear masks, and for DUV or EUV masks. ILT is one of the technologies that can produce high-quality curvilinear, modelbased SRAF. With this technology, the actual shapes of curvilinear assist features are naturally obtained by thresholding an optimized ILT mask that is represented as an image grid, ending up with freeform shapes. In this case, the ILT mask is formed through iterations of an optimization process. The shapes and widths of the freeform SRAF vary from location to location. Such SRAF is expected to deliver a wafer performance close to the optimum defined by the objective function. Nevertheless, the ILT-based curvilinear SRAF is an emerging technology, still on its way to full adoption in production. Therefore, this report focuses on the ILT SRAF obtained differently - constant width SRAF. Constant width SRAF is a more suitable starting point in addressing many practical concerns such as MRC compliance, SRAF printing avoidance, tile boundary stitching friendliness, run-time robustness, and data volume control. The SRAF in this study is characterized by skeletons, each of which is in turn given by the coordinates of ordered “critical” points. These critical points mainly consist of local minima of the gradient map of the objective function. Here the gradient map, roughly speaking, is the partial derivative of the ILT objective function with respect to the transmission values of a grid-represented mask. We will show that the shapes of such constant width SRAF closely match that of the freeform SRAF obtained by thresholding the iterated ILT mask, up to their locations and connectivity, and maintaining the EPE convergence and simulated wafer performance compatible with its freeform counterpart.

Enabled by multi-beam mask writing [1], curvilinear free-form ILT [2], and GPU acceleration [3], curvilinear masks are quickly becoming the norm in leading edge masks, whether for 193i or for EUV, particularly for contact and via layers. An industry standard for compactly representing curvilinear shapes is being developed for SEMI through an industry working group. In it, Bezier, and B-spline "Multigon" formats are proposed to augment the piecewise linear polygons that are supported today [4]. Whether these infinite-resolution curvilinear formats are used or piecewise linear polygons are used, there is a question of what constitutes a high enough vertex density to be of some pre-defined accuracy requirement. With these infinite-resolution curvilinear formats, the vertex density would be lower than with piecewise linear polygons for a particular accuracy requirement. But it is still useful to know what density is theoretically sufficient. This paper explores the concept of rasterization and the mathematical dual between contours and pixel dose arrays given a particular known resolution limit. The paper further argues that curvilinear ILT, practically speaking, is all computed in the pixel domain. And all curvilinear masks, with the notable exception of MWCO masks for 193i [5], are written with multi-beam machines using pixel dose arrays. The paper further argues that all images taken of the resulting masks, whether for inspection, disposition, or for metrology are pictures taken as pixel dose arrays of some resolution with some image processing afterwards. Information theory is a branch of computer science that, among other things, gives insight on how much data is sufficient to represent any particular information content [6,7,8]. More generally, the field covers the idea of digitizing the analog world to some known limit of resolution. Rasterization is digitalization of images that converts from contours, be it piecewise linear polygons, or some infinite resolution curves, to pixel doses of some pixel size and dose range. Contouring is the converse, going from pixel doses to geometric space. By understanding information theory, how curvilinear mask shapes are computed, and how curvilinear mask shapes are generated on

Curvilinear pattern has been introduced as one of solutions for complex and challenging next generation lithography. However mask process correction (MPC) has been developed originally for Manhattan pattern. MPC now is using only orthogonal CD measurement information (so-called conventional modeling) which is not sufficient to represent all information needed to curvilinear pattern. In this reason a new solution for MPC is required for curvilinear pattern. Contour modeling is one of the known modeling techniques, which uses information of many vertices along pattern contour instead of orthogonal CD values. However contour modeling has not been evaluated yet in mass production level. As an evaluating procedure, we introduce a quality assurance (QA) method using virtual SEM contour. By adopting this QA method, we can analyze errors only from modeling itself separated from process induced errors. Moreover, aspect of error budget can be estimated by adding various errors on purpose. In this paper, we present the QA results of contour modeling and the comparison to the conventional modeling. Some discussion and future works will be followed.

Techniques such as Inverse Lithography Technology (ILT) generate complex curvilinear mask shapes which require advanced features and algorithms for efficient execution of the mask data preparation step. For curvilinear mask shapes, there is a strong correlation between the curvature at the point of interest and the bias required in CLMPC correction. Curvature kernels can be used to take advantage of this correlation and can be used to apply a pre-bias to the CLMPC target layer to move it closer to the ideal CLMPC output. Typical ILT results, which serve as input to CLMPC, contain a large variation of local curvatures and a key challenge for effectively applying curvature-based pre-bias is to build a single pre-bias model that works effectively for varying layout curvatures. This paper presents a novel method to calibrate a comprehensive pre-bias model for a given mask process using contour-based modeling techniques. The results demonstrate that a pre-bias model calibrated with this method can offer significant performance benefits and play a crucial role in the development of efficient and accurate CLMPC flows for advanced mask process applications.

Acoustic cavitation continues to be widely used in advanced 193i and EUV megasonic photomask cleaning [1]. However, process challenges remain complex as patterns become smaller [2]. Operating within a narrow process window that ensures both full particle removal and pattern damage control is a balancing act that requires many parameters to be optimized and controlled. These include the transducer type, drive frequency, power setting, flow rate, gas concentration, temperature, chemistry, and transducer position [3, 4, 5, 6, 7]. While batch processing may be more economical for less critical cleaning steps, advanced lithography processes rely on single photomask cleaning technologies because of the increased need for within mask control. Improved cleaning uniformity is achieved through the continuous movement of the photomask and transducer. In-situ measurement of the acoustic field is required to correlate acoustic parameters with cleaning performance. Previous work introduced a photomask-shaped cavitation sensor array wired to a cavitation meter which characterized how acoustic cavitation varied with parameters such as drive frequency, generator power, transducer distance, and sensor position correlated with cavitation pressure under a static condition [7]. In this study, the technology was extended by developing a wireless sensor array to incorporate the dynamic effects of the photomask rotation and the transducer arm translation. The acoustic pressure uniformity across the photomask was evaluated for varying parameters, including mask rotational speed, transducer arm speed, and exposure time. Pressure measurements of the direct field (P0), stable cavitation (Ps), and transient cavitation (Pt) exhibited distinct signatures that may be indicative of cleaning performance, specifically particle removal or pattern damage. The high costs of advanced photomask processes have demanded a zero-defect requirement, a constraint prevalent across the semiconductor industry [8]. The study aims to better understand how process variables affect acoustic performance to establish a process control strategy.

Tin (Sn) and Lead (Pb) particles released from the EUV scanner can contaminate the EUV mask causing serious yield and throughput problems. These contaminants can worsen during EUV exposure and become difficult to remove, leading to damaging the EUV mask in the process. To effectively remove contaminants without substrate damage, it is necessary to understand the removal behavior of the contaminants. In this study, the removal behavior of Sn and Pb particles was studied by simulating the EUV exposure heated by rapid thermal annealing. The removal forces between the thermally aged Sn and Pb particles and EUV substrate surfaces were quantitatively measured using atomic force microscopy (AFM). With the thermal aging time, the contact area of the deformed particle increases which requires a high removal force. After particle removal, the footprint of the contaminants was investigated to understand the surface quality of where the particles sat under the various exposure conditions. This study helps to better understand the adhesion mechanism and removal behavior of thermally deformed Sn and Pb particles on different EUV substrates.

The high-reflectance phase-shifting mask (HR-PSM) is studied for patterning 36nm-pitch logic contact holes and compared with other mask absorbers in terms of imaging performance (ILS, LCDU, MEEF, etc.) and exposure dose. To this end, wafer-data-calibrated EUV resist models for CAR and MOR are used. Our simulation results show that a HRPSM produces dark-field images at large mask CD. However, as mask CD decreases, the tone of the images is reversed and bright-field images of good contrast can be generated. Based on this observation, a HR-PSM plus MOR patterning approach is proposed for through-pitch logic contact hole applications with a minimum pitch equal to 36 nm. We show that this approach demonstrates multiple enhancements in terms of through-pitch performance and enables us to extend the practical resolution of logic contact holes below the pitch of 40 nm using the 0.33NA EUV scanner.

As EUV lithography transitions to high volume manufacturing, actinic inspection tools at 13.5 nm wavelength are attractive for understanding the printability of EUV mask defects, as well as for in-fab monitoring for possible defects emerging from extended use. Coherent diffractive imaging (CDI) is a lensless imaging technique that allows for phaseand-amplitude, aberration-free, high-resolution imaging in the EUV. Moreover, sources based on high harmonic generation (HHG) of ultrafast lasers are a proven viable coherent light source for CDI, with flux sufficient for rapid large-area inspection and small-area imaging. By combining CDI and HHG, we implemented actinic EUV photomask inspection on a low-cost tabletop-scale setup. Moreover, we propose and demonstrate a solution to the challenge of ptychographic imaging of periodic structures through careful illumination engineering.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay and defectivity. For overlay, we present results on stability and also discuss new methods to further address high order distortion. For defectivity, we review random defect generation, particle adders and mask inspection methods. In addition, we also discuss Canon’s recent involvement in the New Energy and Industrial Technology Development Organization (NEDO) project and its goals related to logic devices. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

Nanoimprint lithography, NIL, is an attractive lithography technique for fine feature pattern fabrication, simple process and low cost of ownership. NIL templates play an important role because templates define the resolution of NIL process. In this paper we discussed fine feature hole template fabrication and their performance such as CD uniformity and image placement along with the feature size and duty ratio. In addition, we proposed to apply LELE(Litho-Etch-Litho-Etch) method to fabricate fine feature hole templates and discussed their performances.

Building accurate models for Mask Process Correction (MPC) is indispensable for manufacturing masks for advanced wafer production nodes. In recent years, contour-based model calibration is being increasingly studied as a supplement to standard gauge-based modeling. In this paper, we demonstrate a data processing flow for contour calibration of MPC models to overcome the issue of noisy input contours by averaging the measured contours of repeating patterns within the SEM image field-of-view (FOV). This method not only averages out the statistical noise in the incoming FOV contours, but also allows us to make the model calibration process more efficient.

Etch bias correction method is essential to meet the critical dimension (CD) uniformity requirements for mask process correction (MPC), and it has evolved along with the development of process technologies. For matured nodes, rule-based etch bias corrections are adopted. However, this method suffers from limited accuracy and cannot meet the tight CD controls requirement over various patterns for advanced process nodes. To model nontrivial etching process effects such as the aperture effect and the microloading effect, Ref. 1 proposed a variable etch bias (VEB) model. This edge-based semi-empirical model has been widely used in many applications in production and demonstrates good model fits for various layout features and process conditions. In addition, compared to physical etch models, the VEB model is easier to calibrate and requires less runtime. However, for more advanced nodes with EUV masks, and high sensitivity photoresists, only a complex VEB model might be able to meet the precise CD accuracy requirements. The main source of error for the VEB model is the residual error that results from all aspects of the etching process, and a semi-empirical model cannot fully capture it. To overcome this challenge, we propose a neural network assisted etch (N2E) model for MPC. The N2E model is a two-stage etch model that contains a VEB model followed by a neural network assisted model (NNAM).2 With NNAM, the VEB model in the two-stage N2E model can be simpler than the conventional VEB model while maintaining the same accuracy. In addition, compared to the conventional VEB model, the calibrated N2E model is able to achieve a smaller root mean square error (RMSE) between the measured and predicted etch CDs. Besides, the N2E model produces a small RMSE for the validation dataset and generalizes well. Therefore, the N2E model has the potential to simplify the VEB model part and improve the overall accuracy of MPC.

Photomasks for the semiconductor chip production are typically written with either laser- or e-beam writers. Laser tools have the advantage of fast writing speeds and are overall more cost effective than e-beam writers. On the other hand, ebeam writers achieve significantly better mask accuracy in terms of minimum Critical Dimension (CD) and CD uniformity. Despite the accuracy disadvantage of laser writers, on average, they account for approximately 70% of all masks delivered by the mask industry, during the years between 2018 and 2020. The widespread use of laser writers and their technical limitations make them excellent candidates for Mask Process Corrections (MPC). This work investigates the feasibility of using MPC, developed for e-beam writers, with minor modifications to laser writers. It will be shown that adding an anisotropic component to the models used for e-beam lithography is sufficient for simulating the laser tool signature. With such models, MPC provides an opportunity to expand the application space of laser tools into CD ranges, not possible without MPC and enables tool signature matching between mask writers similar to that used for e-beam writers.

Fast and non-destructive non-imaging metrology of nanostructures is crucial for the development of integrated circuits and for the corresponding in-situ metrology within fabrication processes. Stochastic variations related to the gratings local period (line edge roughness, LER) and line width (line width roughness, LWR) are of special interest due to their key role for the minimal achievable structure size. Non-imaging metrology approaches taking these statistic variations into account are quite limited. For scatterometry, models predict a change of the grating’s diffraction efficiency according to a DebyeWaller factor but only in the non-zeroth diffraction orders. The authors perform simulations of nanoscale gratings that suggest an influence of LER and LWR on the reflectance (zeroth diffraction order efficiency) which motivate an extended study on LER and LWR measured by spectrally resolved EUV reflectometry here described as EUV spectrometry. The authors present reconstruction results of nanoscale gratings measured with a compact spectrometer utilizing extreme ultraviolet (EUV) radiation emitted by a discharged-produced plasma (DPP) EUV source. The use of two sequential spectrographs, one for the reference measurement of the source spectrum, the other one for the measurement of the spectrum after sample interaction, combined within the experimental setup allows to measure the broadband reflectance with 2% relative uncertainty of samples under various grazing incidence angles. The method offers a proven sub-nm reconstruction accuracy for critical grating parameters. Within the presented study, the measured samples are dedicated test samples, fabricated to exhibit well-defined LER and LWR at different grating periods and linewidths. In addition, the samples are also cross-characterized by the Physikalisch-Technische Bundesanstalt (PTB, Berlin). Experimental and simulative results are discussed to derive approaches to include LER and LWR as parameters in the physical model for reconstruction.

In all investigations that we performed over the past years; it has been clearly demonstrated that the off-line mask-to-mask overlay as determined on the Zeiss PROVE tool correlates very well with the on-wafer measurements. It all started off with a correlation study utilizing wafer alignment marks. Wafer alignment marks are metrology structures that can be read out inside ASML scanners by the wafer alignment sensor. In that work, the impact of the reticle alignment marks required to align the mask inside the scanner was incorporated as well. An excellent correlation (R2 < 0.96) was shown with an accuracy of 0.58-nm. This result was achieved after carefully setting up an experiment in photoresist and by ruling out any other additional overlay contributors other than mask and the scanner baseline overlay performance. After this initial success, we continued the investigation by considering µ-DBO (Diffraction Based Overlay) metrology targets that can be read out on an ASML Yieldstar (YS:375) overlay metrology tool. In this work, the complexity of the experiment was increased. Instead of using only photo resist, an industry relevant process Litho-Etch process flow was selected. The mask was written on a state-of-the-art writing tool (EBM-9000). Again, excellent correlation coefficients (R2 < 0.92) were obtained. This time within the sub-nanometer range at wafer level. During the execution of that work, an error source that contributes to the small mismatch (< 0.14-nm) between mask and on-wafer measurements was addressed: the sampling scheme difference of the signal generating areas. While the PROVE tool has been designed to measure local (feature) placement errors, this is not the case for an overlay metrology tool or the scanner wafer alignment sensor. For the latter two metrology systems, a position is obtained from a much larger region of interest (ROI) for which local placement errors are averaged out. The observed mismatch can easily be mitigated by increasing the number of PROVE measurements with a small ROI to match it with the ROI of the overlay metrology tool or the wafer alignment sensor. While studying the increasing number of local registration measurements by the PROVE tool, an interesting observation was made. The way the mask had been written on the mask e-beam writer seemed to be reflected in the residual local registration measurements! Stripes were observed that appear to be running across the full width of the mask. Since the typical dimensions of the stripes at wafer level are small compared to the areas that are used for overlay measurements and/or wafer alignment measurements, they are hard to detect on wafer by using optical techniques. In this follow-up work, we explore the correlation between mask registration measurements and the on-wafer measurement for individual device features. This means that we make another step-in complexity, the length scales of interest are now significantly below the typical dimensions of an overlay metrology target. To continue the correlation study, a large field of view SEM is required to measure the relative positions of the device features. We show that the way the mask has been written can indeed be found back on wafer! Although the local placement errors for a single logic device feature is in the order of ~0.5-nm at wafer level, we show that the correlation between mask measurements and wafer measurement still holds. This enables an interesting new application space that is addressed in the current paper.

In this contribution we describe an experimental study measuring local CD uniformity (LCDU) of DRAM contact arrays on both an EUV reticle and corresponding exposed wafer. Direct measurement of LCDU from reticle SEM images is compared to the reticle component of wafer level LCDU determined by decomposition of wafer level only data. The goal of this study is to better understand the contribution of reticle LCDU to wafer LCDU and the degree of accuracy to which the reticle component can be determined without reticle metrology. In addition to comparing the two methods of determining mask LCDU we use the measured mask contours as input to ASML Tachyon lithography simulation software and compare the simulated and experimental wafer CDs, CD distributions, and local MEEF. This gives some insight on the proportion of the mask variability coming from the variation of absorber edge placement. Three different DRAM contact array pitches are examined 36, 38 and 40nm. Each array contains a registration mark to allow each individual contact to be reliably identified. Reticle SEM images are collected for 20 locations for each pitch and the three highest and three lowest LCDU locations are selected. These six selected reticle locations (per pitch) are measured by SEM in resist at 117 die across a CDU wafer (i.e. a wafer where all die have the same focus and exposure dose). Each wafer location is measured twice. With this dataset the reticle and wafer LCDU, CD and placement can all be measured and correlated, and the reticle, metrology and stochastic components of the wafer LCDU can be determined. Metrology is performed using ASML Brion’s MXP to extract contours from both the reticle and wafer SEM images.

EB (electron beam) resist is widely used for the EUV (extreme ultraviolet) mask production. Tighter pitch size and smaller pattern features are required on EUV mask for the next generation EUV patterning. A novel, high dose, positive-tone chemically amplified resist (pCAR) using PHS (polyhydroxystyrene) based polymer has been developed with improved resolution performance as verified by Point-beam writer and Multi-beam mask writer (MBMW). In this study, several high dissolution contrast pCAR formulations were studied under Point-beam conditions to investigate the impact of the chemical blur and the chemical stochastics on lithographic performance. For suppressing the chemical blur in the pCAR after exposure, formulations using larger size PAG (photo acid generator) could improve the resolution performance due to reduced acid diffusivity. For reducing the chemical stochastics, higher PAG loading pCAR and the slower sensitivity pCAR were investigated. Improved resolution and LWR (line width roughness) performances were obtained by these pCAR up to approximately 200μC/cm² under Point-beam condition. On the other hand, the lithographic performance was degraded at 270μC/cm². Analytical results of PAG decomposition ratio by HPLC suggested the possibility that decreased acid generation contrast could degrade lithographic performance when the pCAR sensitivity is too slow. The investigation of different dissolution contrast pCAR showed that higher dissolution contrast pCAR with higher Rmax resulted in improved resolution performance. According to this study, efforts to minimize the chemical blur and stochastics, and to maximize the photoresist contrast were the key factors for designing high-performing, low sensitivity pCAR. The verification results of the ultimate resolution of the representative pCAR with 60nm film thickness were also described in this paper under MBMW and mask process conditions. HP21nm line and space pattern could be resolved without pattern collapse. The small ring pattern with a 10.5nm pattern width was nicely resolved as the smallest feature.

Multibeam mask writers (MBMW) from IMS Nanofabrication developed in the last decade are currently being used for leading edge mask patterning. The ability to utilize low sensitivity resists required to pattern complex mask patterns with good edge placement control made MBMW the tool of choice for leading edge extreme ultraviolet (EUV) mask patterning. The next generation of High-NA EUV masks will require smaller features, more complex figures and reduction of edge placement errors. These requirements may exceed the capability of the current MBMW tools. Recently IMS announced the next generation MBMW tools to address this challenge. This paper will explore the effectiveness of the proposed improvements on addressing High-NA EUV mask patterning challenges.

Chemically amplified resist realized the high sensitivity in semiconductor manufacture by utilizing the acid catalyzed deprotection reaction of protected polymer. One of the parameters reflecting the reaction ability of resist is effective reaction radius of deprotection (R_p). However, R_p cannot be achieved by experimental measurements. Similarly, the concentration of protected units at dissolving point of developer (C_th) cannot be measured as well. C_th strongly related to the generation of defects of resist pattern after development. In the previous study, a simulation model of electron beam (EB) lithography processes from beam exposure to development was constructed. To calibrate the EB lithography model, these parameters must be estimated. Resist pattern taken by scanning electron microscopy (SEM) was used to compare with the simulation calculated resist pattern. The difference between experimental and simulation data was used to evaluate the influence of R_p and C_th on the simulation model. However, during this estimating process, the simulation model must compute every time when R_p or C_th changes. This is time-consuming and the computational cost is high. To reduce the iterative computation, Bayesian optimization (BO) based on Gaussian process regression (GPR) with Matérn covariance kernel was applied to accelerate the optimal pace. BO can optimize the parameter globally and locate the value that worthiest to test. By using BO, the iterative calculation was magnificently reduced from 140 to 35. The probable values of R_p or C_th were found. Furthermore, to prove the ability of BO, the result was verified by grid search method.

This paper presents a novel approach to automatically build frames for 3D chips. These chips may be obtained by stacking multiple dies, but are more often made by a backside wafer processing. This proposed flow works in a single pass and is based on a dedicated constraint-satisfaction software. In addition to the standard placement rules, the different types of constraints used for 3D frames are clearly identified: alignment, overlapping, mirroring. The method to generate separate frames is described. Results and performance obtained in production, for frames involving two different manufacturing processes for wafer front and backside, are detailed.

In this paper, we study the feasibility of direct aerial image measurements with the ZEISS AIMS® EUV tool for quantification of mask effects that impact EPE budget and OPC model accuracy. We demonstrate the application of aerial image metrology for OPC model calibration, pattern shift detection, quantitative mask metrology and for Optical process window characterization.

Photomask technology has contributed to the capability and productivity of integrated circuit (IC) and flat panel display (FPD) manufacturing with the implementation of masks that have improved process capability, margins and yield including but not limited to advanced binary or multi-tone masks and phase shifting masks. These masks are mainly composed of various chrome and phase shift materials deposited onto very high quality and stable substrates made out of fine grade fused silica materials. However, for large-scale masks like those used in manufacturing masks for FPD lithography, the cost and availability of such high quality substrates can be a prohibitive factor for cost effective production. Moreover, it is possible for some layers of these non-IC, large format applications, such very high performance fused silica substrates may not be necessary to meet the lithographic imaging requirements. Therefore, it seems desirable to understand the properties of alternate substrate materials to see if they might be suitable for improving the cost and availability factors in the large format applications. In this paper, we evaluate the optical and physical properties of various non-standard materials including thermal expansion, transmission, flatness and defectivity to better understand how these parameters might impact the imaging of certain layers. We compare major parameters in the lithography process such as CD, registration, displacement, defect printability and chemical durability related to process performance and variation. Moreover, we characterize defects and their impact on process using a general inspection tool and AIMS to assess the importance of certain defect modes especially of the embedded or inclusion type. Bubbles that occur in glass manufacturing process are analyzed and we attempt to classify the patterning impact using simulation and matching with AIMS. Finally, we draw conclusions on the suitability of these alternate materials to deliver a much lower cost mask solution for use in certain large format imaging applications by considering specifically the flat panel process and performance predictions.

The pattern size of semiconductor circuits has been shrunk as technical advances continued. Defect control becomes tighter due to a decrease in defect size that affects the image printed on the wafer. It is critical to the photomask which contained a considerably shrunk circuit and ultra-high density pattern for sub – 20 nm tech devices. In this paper we group two types of rare process defects that think come in vacuum chamber contamination here we also present hypothesis defects mechanism and possible solution.

Nikon has been developing the Digital Scanner (DS), an optical maskless exposure tool with a DUV light source and a micromirror-type spatial light modulator (SLM). Rasterized digital data, essentially huge bitmap files, are used to drive the SLM. The DS enables new applications such as large area printing and chip customization because its digital pattern data are easily modified. Flexible and fast data preparation software was developed for the new applications. As a standard operation of DS data preparation software, a CAD file (GDS or OASIS) is converted into bitmap files. In addition, bitmap file generation by a scripting language is available without a CAD file. This is useful when the CAD file includes a lot of polygons in which each polygon is similar but not identical, resulting in a huge file. As an example of application, a metasurface consists of sub-wavelength periodic patterns with various shapes, which are arranged to achieve the desired optical effect. The shape of each pattern at a grid point can be determined by a computer program, i.e., a pattern generator script. On the other hand, data preparation time can be shortened for periodic pattern which is often seen in semiconductor circuits. We report those data preparation methods for the DS, which have been used for our recent exposure experiments.

High-NA EUV lithography tools are projected to be deployed in HVM by 2025/2026, with the introduction of the N1.4 node. This should allow single-exposure EUVL at 30 nm pitch and below and reduce cost and complexity. One of the main challenges in process control will be the budgeting of depth of focus. With Rayleigh’s equations in mind and considering a relatively thick photoresist needed for etching purposes, an overall focus window of less than 40 nm is expected for high-NA EUV exposures. This is concerning, considering that after almost two decades at roughly constant depth of focus (~100 nm for 1.35 NA ArF immersion and 0.33 NA EUV), we may potentially be dealing with 2-3X lower usable focus range. On top of that - and differently from the DUV case - increasing NA in EUVL exacerbates the impact of complex 3D mask effects which, in a non-telecentric tool with an oblique incidence at the mask, negatively impact best focus shifts across mask pitch and feature CD. In this paper, we look at how to mitigate lines/spaces depth of focus loss across pitch by exploring source, mask pattern and mask stack optimization. Moreover, we compare the best strategy between bright/dark exposures, mask transmissivity, and phase-shifting combined with assist features, resist thickness, and feature orientation. Finally, we compare the optical performance with defect-aware process windows at 0.33 vs. 0.55 NA based upon stochastic resist calibration for generic positive-tone organic CAR, and negative-tone inorganic platforms.

As the medium that transfers integrate circus design graphics to wafer, reticle has irreplaceable importance. DRAM lithography process below 20nm needs multi-patterning technology without EUV adoption, which means more masks need to be used to reach a certain process target. At present, the conventional masks in the industry are divided into phase shift mask(PSM) and chrome on glass (COG) mask. This paper focuses on haze research for COG mask. Haze has always been an unavoidable topic for mask management. In CXMT some traditional haze like ammonium sulfate has almost disappeared. However, several COG masks in a set of products still suffered haze issues which caused very short lifetime. This haze has very typical characteristics, which is different from ammonium sulfate haze or molybdenum oxide haze widely recognized in worldwide. Based on the mask layout, the correlation between haze and mask pattern was explored, as well as the specific location relationship between haze and line in the pattern. Two different haze types named type L and type C were identified based on their aggregation map, of which the growth rate and frequency were tracked, and the chemical sources were identified based on the microscopic results. Based on what we found, the mask manufacture process in mask house and mask management process in fab were optimized to maximum mask lifetime.

EUV is considered to be the promising lithography technology for the continuous evolution of semiconductor nodes. However, the mainstream ArF/Immersion lithography are still used in current industry and keep continual develop process node ahead. The performance of the mask determines the quality of lithography process directly. Litho-images on wafer come from mask pattern. The quality control of exposure image like local CD uniformity(LCDU) become the most critical factor except the optical proximity correction (OPC) effect. In view of the great challenge of LCDU improvement of small hole pattern on the of 1xnm process research and development. How to use ArF/Immersion lithography technology to improve the performance of hole pattern is this research topic. A new high transmission phase shift mask(HT-PSM) developed on the common ArF/Immersion platform and compared with the performance of normalized image log slope(NILS), mask error enhancement factor(MEEF) and depth of focus (DOF), found that 30%HT-PSM has advantage over the hole pattern. In this paper, research for positive tone development(PTD) and negative tone development(NTD) on high transmission phase shift rate. Different transmission manufacturing processes and application of 30%PSM are compared with conventional 6%PSM. At the same time, litho-image exposure on wafer can be measured and compared in actual research and development. Combine the results of resolution and physical failure analysis(PFA) results, it has higher resolution and good section-cross profile. Meanwhile, the LCDU is improved about 10% batter than conventional PSM mask, which makes an effective contribution to the research and development of advanced process.

The interaction of matter and light can be described based on optical constants, shortly called δ&β. These constants provide the fundamental basis for the design of any optical system. In the Extreme Ultraviolet (EUV) spectral range, however, the existing data for many materials or compounds is very sparse, non-existent or exhibit considerable discrepancies between different sources. This is further complicated since the scaling effects stipulate the optical response of a thin film to differ from bulk. Oxidation, impurities or interdiffusion significantly affect the optical response of a system to EUV radiation. For this reason, the Physikalisch-Technische Bundesanstalt (PTB) is establishing a new database in cooperation with other European partners. This database, designated as the Optical Constants Database (OCDB) can be accessed online freely (OCDB.ptb.de). This data collection shall support further development of various fields from new metrological techniques, like EUV scatterometry to computational lithography in the EUV. This is demonstrated exemplarily here by the interplay between δ&β and the dimensional parameters with respect to a structured TaTeN EUV photomask. It is equally important either direction, to derive structure parameters from the measured EUV scattering as vice versa to predict the EUV response from the geometrical structure. In addition, the impact of varying δ and β on the expected imaging performance will be investigated by simulating typical lithographic image metrics like Critical Dimension (CD), best focus position, image contrast (NILS) and non-telecentricity for the imaging of through pitch L/S and 16 nm vertical Lines with 32 nm pitch in a NA=0.55 scanner for TaTeN mask absorber as typical representatives of high-k absorber materialsand as an example of the effect on imaging simulation.