The emerging multichip packaging technology offers significant advantages in miniaturization faster electrical performance efficient thermal performance lower cost and significantly improved reliability. Newly available materials and processes have stimulated multichip applications ranging from low-cost consumer electronics and automotive modules to advanced aerospace and supercomputer applications. Avionics multichip modules share the same systems integration issues as other applications: optimum partitioning seamless CAD/CIM tools testability and repairability strategies cost-effective manufacturing availability of vendor support technologies and reliable packaging for long life in environmental stresses. This paper discusses state-of-the-art avionics multichip modules industry developments required to enable wider utilization and evolutionary extensions into next generation technologies.

The Strategic Defense Initiative and other space programs have accelerated the requirement to put fast powerful computers with large memory requirements into space on various satellites. Operation during launch and in space environments places some challenging requirements on siliconbased electronics. They must survive large thermal and mechanical shocks and exposure to radiation. This paper presents one of the approaches taken to date to build spaceborne computers with high density multi-chip packaging technology.

A discontinuity has developed between the densities available with ULSI circuits and printed circuit board assemblies. Multichip module (MCM) technologies are poised to bridge that gap. Properly designed 3-D MCMs can deliver the compact size and high-speed of near wafer scale integration but notwithout significant electro-mechanical design challenges. This paper explores the natural constraints shaping future high speed interconnect design. 1. The Problem The transmission of subnanosecond signals alone is not difficult. Difficulties arise when one attempts to assemble multiple circuits into a system that need to transfer information at subnanosecond speeds. The system design puzzle in figure [1] depicts the problem faced by computer designers . '' Success is measured by how cost effectively one is able to interconnect and integrate the processor cache main memory data I/O cooling and the DC power system. Solutions to this challenge are evolving at a revolutionary pace. The subnanosecond pulse shown in figure [2] is representative of the information signals transferred between logic circuits of the system. Signal rise and fall times of less than 100 picoseconds are common today. One could slow down the pulse edge rise time to alleviate current switching problems while sacrificing system performance. Lowering voltage swings will also assist with the current switching demands. 2. The System Volume All the components that go into a system occupy space. Less space translates into hiher speeds and lower materials costs.

Gallium arsenide monolithic microwave integrated circuits(GaAs MMICs) have been developed to operate at 1 to 30GHz. Their packaging technologies are classified into several levels ranging from a microwave package design to an interconnection technology. This paper reviews the status of and trends in the packaging tech nologies for GaAs MMIC modules.

The history of the integrated circuit has shown that complexity can increase while cost per function decreases. The driving force behind the development of Multi-Chip Modules (MCM) for use in the military environment is primarily one of reduction in system volume and weight. As has been the case with IC''s monolithic integration improves the overall system reliability through a reduction in the number of wirebonds increases the system operating speed through a reduction in propagation delay resulting from much shorter interconnects and reduces the overall system cost per function by eliminating the cost of assembly of the subassembly packages. The successful implementation of High Density Multi- Chip Interconnect (HDMI) technology requires a system level approach to packaging which mandates that the system designer take into account the interface between integrated circuits and the package matching impedance to achieve the best possible system performance. Large HDMI substrate designs have been produced which replace older printed wiring board technology with a significant reduction in system volume and weight and at a reduced cost per function when compared to the older methodology.

As the rise time of digital pulses is reduced to the subnanosecond range the skin effect becomes an important issue in high-speed digital systems. In this paper the various approaches (theoretical and experimental) which have been taken to study the skin effect are surveyed. Various methods that accommodate the skin effect phenomenon into conductor design rules for high-speed digital systems are examined and compared. The resulting impact of these accommodations on high performance ULSI/VLSI multichip packages is addressed.

Multi-chip modules (MOM) have recently received much attention because they facilitate high density and speed packaging of electronic systems. MOM''s tradeoffs are examined here for logic and memory subsystems using a newly developed package system simulation methodology. MOM''s are optimized for CMOS technologies using the simulated annealing algorithm. Parameters for optimum MOM designs are shown to separate clearly in the response space. Based on this guidelines for computer system integration with MOM''s are set up.

Technology capability in packaging interconnects has outrun the design capability. Here ''design" is used in the sense which includes setting and meeting performance metrics as well as performing geometric layout. Limitations on design capability are due in part to lack of detailed understanding of mechanisms or lack of " expertness" available to incorporate into a design system. Progress in design capability will be discussed capability gaps noted impact of drivers examined and practical examples given.

The limitations ofmetal interconnections in MultiChip Modules (MCM''s) are examined primarily with respect to their bandwidth arid propagation loss. Comparison is made with the alternative ofemploying optical interconnections. Some of the technical issues which lie ahead to make a Photonic Multichip Package (PMP) possible are explored. Certain organic materials are identified as promising candidates for implementing optical interconnections. These are found to be interesting because of their low deposition temperatures and because they lend themselves to fabrication by techniques that are already finding acceptance for metal interconnections in thin film MCM manufacturing.

It is now generally recognised that the performance of an electronic system is governed by the choice of packaging technology. Never before have the technical and financial implications of a packaging technology choice been more critical and never before has technology interdependence or industry globalisation made the choice more difficult. This paper is aimed at examining the choices available and the system issues resulting from the move from single chip to multichip packaging.

The architecture of an integrated CAD system to automate the design of optoelectronic systems is presented in this paper. Optoelectronic technology with free-space optical interconnects offers the potential to build high-performance computers. As this technology matures increased design complexity will mandate the use of CAD. CAD tools and specifications for the design process of optoelectronic systems are described. The proposed architecture extends existing CAD technologies to optoelectronics.

Passive interconnection networks are important for three reasons. First they represent an increasing percentage of the cycle time as the active devices are " scaled" . Second they contribute to di/dt coupled and reflected noise. Third higher clock frequencies are making the interconnection medium a more effective radiator especially in the 30 MHz to 1 GHz range where limits have been established by regulatory agencies such as the FCC. Approaches to understanding these phenomena will be highlighted.

The high signal density clock rates and output slew rates associated with state-of-the-art digital logic renders design verification of modern high performance digital systems to be increasingly difficult and critical. The electrical and mechanical design of these circuits must be analyzed in conjunction with the analysis and simulation of the underlying logic design to result in operational and manufacturable systems. This paper will describe several useful techniques relevant to verification of such systems including static timing verification transmission line simulation and crosstalk analysis. The principles underlying these techniques will be discussed and results for sample algorithms given.

Future communications networks will be required to provide the switching of very broad-band digita'' channels (typically 155. 52 Mb/s or higher) for as many as 60 customers. Power consumption and cable management are a major factor in the systems level design considerations. It is shown that through the use of ultra-low threshold laser diode arrays optical fiber ribbon cables and a thoughtful packaging strategy significant electrical power advantage can be accrued over conventional electrical interconnection approaches. 1_a

The generation and characterization of both pulsed and CW high frequency waveforms using picosecond photoconductors are reviewed. A time-domain network analyzer which uses optoelectroni c techniques for on-wafer monolithic microwave and millimeter-wave integrated circuit measurements is described. An optical-microwave intermixing teclmique has been applied to phase-lock a free running microwave oscillator with picosecond laser pulses.

This paper proposes a new formalism to classify distributed systems. Traditional tools like queuing theory Markov chains and perturbance analysis assume linear system behaviors and are used to characterize steady state operation meaningful only if the dynamic transients are disregarded. An approach based upon methodology used to characterize nonlinear chaotic systems is introduced. A simulation model a mesh of processors with distributed routing is used to demonstrate typical behaviors including chaos.

There are many applications in which both electronic and optical interconnections are possible. These include most tasks currently being adequately performed by electronic interconnections. Optics must win such battles overwhelmingly to gain acceptance. We argue here that there will be other situations where electronics can not conceivably compete. The disadvantage of these situations is that their markets and technologies are not well developed. The advantage is that these are sure wins for optics. Advantages in fanin/fanout three dimensionality absence of such electronics problems as EMI ease of making/breaking connections avoidance of transduction smart interconnection and virtual computing are explored briefly.

We present several optical interconnection structures for multiprocessor applications. In general the communication paradigms used in multiprocessor systems can be classified as either broadcast or or switched point-to-point systems. It has been suggested that it is desirable to additionally support multicasting and simulcasting modes of communication. These modes are not widely implemented in electronics due to the complexity of their implementation. Using a self routing technique called coincident pulse addressing such structures can be realized efficiently in optics. In this paper we address two issues. First we demonstrate that the technique can be implemented with sufficient reliability and scale in technologies which are appropriate for computing applications. Second we discuss the application of these networks to multiprocessor systems. Using linear structures we demonstrate broadcasting multicasting and simulcasting communication networks. By using two dimensional structures we demonstrate multi-port memory access permutation networks and multiple sender versions of the linear networks.

The architecture of Array Processors with Pipelined Busses (APPB) has recently been proposed as a new hybrid optical-electronic parallel computer architecture which uses messagepipelined optical busses for interprocessor communications. In this paper we show how pipelined messages can be interleaved and overlapped so that the communication capacity of a pipelined optical bus is fully utilized. We also show how to align communicating processors in twodimensional APPB so that only one bus cycle is needed for routing messages between any two communicating processors in a given communication structure. Finally a comparison of the cornmunication bandwidth of a pipelined bus with that of an exclusive access bus is given which shows that the pipelined bus achieves an asymptotically linear in number of processors on the bus improvement over the exclusive access bus.

An optically interconnected multichip module designed specifically to meet the demands of high performance processor array systems is proposed. The system consists of computer generated holograms GaAs laser array chips and Si VLSI chips containing processing elements and integrated photodetectors. All components are incorporated into a package (similar to an existing multichip module design) with a water-cooled heat sink. All intramodule chip-to-chip connections longer than a particular line length and all intermodule connections are implemented optically. Limitations on power dissipation bandwidth connection density and alignment tolerances are discussed. The performance is compared with both electrical thin film interconnects and guided wave optical interconnects.

In despite of the extensive class of computers a break-through of the implementation of Optical Interconnects in the Massive Parallel versions has still not taken place. Only a top-bottom approach will give a thorough insight where those techniques will satisfy forcing researchers in this area to cover almost all the knowledge of topics related to Computer Archi- Lectures Transport media Electro-Optic and Opto-Electronic technologies. Interconnecting Printed Circuit Boards through an Optical Backbone could be the first step

In this paper wepresenttwoarchitectures ofhigh speedalloptical multistage interconnection networks anddiscuss how emerging opticaltechnology canprovide solution to switchingproblems which arise in telecommunication and supercomputersystems. The architectures support circuitswitched and packetswitching and are based on alloptical bistable device which constitutes an essential component of switching units. Various design issues related to optical clock generation its distribution data synchronization intensity restoration and power requirement are also discussed.

Optically coupled three-dimensional (3D) memory system is newly proposed for ultra fast parallel processing in computation. Several memory layers with LED''s and photoconductors are stacked and the data transfer among these memory layers is performed by optical coupling in this memory system. Two kinds of new intelligent memories an optically coupled 3D common memory (3D- OCCM) and an optically coupled 3D content addressable memory (3DOCAM) are employed for simultaneously sharing data and implementing parallel data inspection.

The technical feasibility and the performance of packaged systems with free space optical interconnections for parallel computing are analyzed. System issues such as volume power consumption optical properties of interconnection elements yield problems and noise limitations are considered and their dependence on the existing and future technological constraints are outlined.

General Electric Corporate Research and Development Schenectady NY 12301 Technology Overview GE''s High Density Interconnect (GE-HDI) is an excellent solution to the digital multichip packaging problem as well as offering solutions to other difficult system interconnect problems in analog power microwave display and sensors. While it is a rapidly evolving technology it has been applied successfully to a broad class of over 20 applications. It offers the highest density performance reliability and in addition rapid prototyping repairability and extension to tomorrow''s technologies such as three dimensional assemblies. The General Electric High Density Interconnect (GE-HDI) process is a proprietary process for interconnecting bare chips bonded to a ceramic substrate with ultra-fine metal lines drawn with the help of a computer-guided laser. The chips almost touch one another thus achieving silicon area densities for the module that can reach 90. The lines are ultrafine but also ultra-reliable thanks to the nature of the process. The interconnect is an overlay of multiple levels of copper polymide placed on top of the chips. The connection to the die is vacuum sputtered metal followed by plated copper. With the complete absence of conventional die interconnects such as wire bonds tape or solder bumps which are the greatest cause of failures reliability as well as performance are greatly enhanced. In actuality the HDI process is an extension of wafer processing which reliably makes hundreds of thousands of

Projection direct imaging uses a laser-written liquid crystal light valve serving as an erasable mask to create multiple copies on photoresist coated substrates using projection photolithography. This technology is applicable to printed circuit manufacture high-density electronic interconnection and packaging.

The proliferation of systems designers using optical components to improve the performance of their systems has resulted in the need f or an integrated design and analysis tool. IDEAL (Interactive Design and Electro-Optic Analysis Liaise) has an interactive menu driven interface with graphical representation of systems or components under design. IDEAL allows a mixture of different layers of abstraction in the descriptions. Component libraries geometric description editor and various analysis tools are also available along with an I/O library to integrate your own analysis or data.

Interconnections not only " cost" systems in terms of dollars performance and space but they also " benefit" systems because they allow them to be partitioned into smaller more manageable subsystems. The physical design process needs to more explicitly characterize system partitioning impacts and evolve system design so as to balance these " costs" and " benefits" .

HWSI''s impact on the size weight power cost speed and reliability of advanced systems is well recognized. Using the HWSI designers have profound opportunity to create innovative components and systems. However the HWSI so far is not accessible to most of them because of its high cost in prototyping and low-volume manufacturing. To solve this problem a proposal is being studied to develop a compact integrated prototyping center which delivers semi-custom HWSI modules within hours after the design is finished. The center conducts three major tasks: 1) fabricating interconnects by optical scanning and chemical etching 2) developing a solder mask by optical scanning and 3) soldering flip-chip assemblies by pickandplace and reflow. Through system simulation the proposed design for the center requires only eight automated units while maintaining a reasonable prototyping turn-around time (5 hours for the first module and 13 hours for a batch of 20 modules) . The corresponding packaging cost for each 1 inch square module ranges from $150 to $500 depending on the annual prototyping volume. A!

A study was conducted to understand the effects of niold conipound flow behavior on disturbed wire occurences in plastic packages. Fluid niechanics considerations were used to determine the type of flow effects of the boundary layer shear stresses and velocity profile to the bond wire. Short shots and the use of colored pellets helped in the visualization of flow patterns. A plastic deforniation of beanis niodel was used to estimate the amount of force required to sway a wire and conipared to the force calculated from plastic flow velocity distribution.

A unique method has been developed for interconnecting a GaAs semiconductor device to an Application Specific Integrated Circuit (ASIC) chip. The device has 400 control points on a 25 im pitch. A silicon interconnect chip with cantilevered gold beam leads having the same packing density as the GaAs device and ASIC chip was designed to " bridge" the space between the two. Special photolithographic steps had to be developed to fabricate beams 250 pm long X 9 tm thick. The methods for fabricating the bridge chip and its final assembly will be discussed.