The capture and emission of electrons and holes into and from single, individual interface traps are studied in micron-sized MOSFETs. The trapping process creates discrete switching in the source-drain resistance, which is observed as a random telegraph signal in the source-drain current. The number of traps may be counted in quantized transients observed after pulsed filling of traps. The average rate time constants for the trapping process are consistent with Coulomb repulsive centers, i.e. acceptors near the conduction band edge and donors near the valence band edge of silicon. The capture and emission rates are strongly activated by an interfacial barrier. The 1/f noise power spectrum is quantitatively described by the random telegraph signal of several interface traps. Individual traps induce Fermi level pinning in the 2D SiO2-Si system.

The incorporation of small amounts of fluorine in the silicon dioxide during thermal oxidation has resulted in substantial changes on its electrical and physical properties: The oxidation rates are increased, the breakdown strength is raised, and a substantial improvement of the radiation response of Metal-Oxide-Semiconductor (MOS) structures is observed. In the latter, the improvements occur in the generation of positive oxide charge and interface traps, and the long-term post- irradiation buildup of the interface traps is either suppressed or greatly reduced. These results beyond its scientific implications are of significant technological importance towards the development of advanced MOS technologies.

The rapid increase in the development of new VLSI structures indicates that the most cost effective way to design semiconductor devices is using numerical simulation based on sophisticated bi or three- dimensional models. In this paper we detail the solution of the bi- dimensional Poisson equation applied to a MOSFET in thermal equilibrium. This problem, although quite simple, can give detailed information about the operation of submicron devices in certain conditions, and serves as a good introduction to the study of the dimensional effects in the operation of semiconductor structures. We obtain numerical results and establish some comparisons between devices with channels length of 5.0 micrometers and 1.0 micrometers .

Sandwich structures composed of various contact materials and Ti:W barrier layer are compared. Their contact resistance and reliability datas are given. The step coverage of APCVD borosilicate glass (BSG) is described in detail on a new graphic representation. BSG is shown to have superior step coverage properties. Recommendations for optimal void free deposition are described. The application of these layers is illustrated in a 1 micrometers double level metal process.

A simple analytical model for the potential drop in the silicon substrate on thin film SOI MOSFET''s is developed. The model clearly show the dependence of this potential drop on the process parameters. The analysis is supported by numerical simulation from PISCES. A very good fitting in the depletion region and a reasonable agreement in the accumulation and inversion regions is obtained. The effect of this potential drop in the substrate on the threshold voltage is analyzed and it is shown that when the back oxide thickness decreases, the influence on the threshold voltage increases in the same proportion. It is also shown that if we don''t have a good control of the back-oxide/substrate interface, it will be difficult to know the value of the threshold voltage deviation because of its high sensitivity to changes in interface charge density.

This communication details the choice of a CMOS/VDMOS processing technology and of a design methodology adapted to the realization of a monolithic solid state, high-side power switch for automotive applications. Particular emphasis is made on the latch-up problem and the developed solution that provides the necessary immunity. The devices, circuits and functions made possible by this technology are also described.

In order to improve the voltage handling capability of high voltage and power devices, an efficient technique based on the deposition of a semi- resistive layer acting as a field plate is proposed. The complete design of a high voltage planar transistor (1500V) using a SIPOS layer on SiO2 film is extracted from bidimensional numerical simulations. The evolution of breakdown voltage BVcbo versus critical parameters as oxide thickness, field plate length and field plate-stop channel distance is calculated. A good agreement between theoretical and experimental results is obtained. The breakdown voltage achieved by the devices is near 90 of the ideal planar breakdown voltage without any damage for other electrical parameters.

This review emphasizes controlled shallow doping of GaAs by ion implantation and its limitations to the state-of-art GaAs IC technology. It discusses the electrical activation behavior of implanted silicon in GaAs upon subsequent capless or silicon nitride capped rapid thermal annealing (RTA). It is demonstrated that atomic H diffuses into the implanted region of GaAs during PECVD of a Si3N4 cap and the H retards the electrical activation kinetics of the implanted Si. Applications of ion implantation to achieve buried-p layers as well as isolation between neighboring devices in GaAs are also briefly discussed.

Device scaling trends have resulted in smaller devices having new performance and reliability problems. Hot electron effects and difficulties in obtaining precise device structures and performance are among the most severe. Sophisticated and novel device structures incorporating advanced knowledge of device physics combined with better process uniformity and precision are required to overcome these problems. Fabrication of such structures demands new process technology to form the desired structures. An ion implanter has been designed specifically for submicron applications and for construction of advanced three-dimensional (3D) device structures. The instrument used a programmable goniometer as the target positioning system. This versatile endstation is designed to meet the emerging requirements for flexible target positioning and repositioning in submicron applications and other 3D devices. Some contributions of these new implanter features to device performance will be discussed. Specific examples of source-drain engineering applications (LATID - Large Angle Tilt Implanted Drain and LATIPS - Large Angle Tilt Implanted Punch-through Stopper devices), 3D structure applications (trenches), and channeling control applications are identified and discussed. The implanter is described together with some of its performance specifications.

a-SixGe1-x (x equals 0.70) thin films were deposited by RF- sputtering at a constant substrate temperature of 200 degree(s)C. By adding oxygen or ammonia to the sputtering atmosphere, amorphous films containing oxygen or nitrogen could be obtained. The incorporation of these elements was ascertained by IR spectroscopy which revealed the characteristic features of oxygen and nitrogen bonded to silicon. The IR spectra also showed that hydrogen incorporation has been achieved for the films prepared with ammonia. The increase of oxygen and nitrogen content shifts the peak position of the corresponding main absorption bands towards higher energies. The absorption edge and the optical gap are strongly dependent on oxygen and nitrogen incorporation. The increase of oxygen and nitrogen content increases the optical gap. The room temperature DC conductivity decreases by several orders of magnitude with oxygen and nitrogen incorporation and reflects the widening of the optical gap.

GaAs/AlxGa1-xAs isotype n heterojunctions have been used as microwave rectifier diodes and recently suggested for hot electron launching. Namely, direct injection of electrons into the upper valleys of GaAs along the (100) direction has been referred, as a means of providing suitable initial conditions for the formation of electric field impoverishment modes. We now consider, by numerical simulation, the series association of the GaAs/AlGaAs heterojunction as the cathode injector of a GaAs Gunn diode. A thermionic injection type model is used to establish the electron conditions at the cathode contact on the GaAs side. From there on to the anode, electron transport is calculated by using a matrix that is calculated by Monte Carlo. It takes into account ballistic effects and is framed by Boltzmann''s transport equation (BTE). Simulation results predict an improvement in the efficiency of microwave power conversion in the transit time mode applications, by using hot electron launching. Optimization corresponds to an Al content x equals 0.3 in the ternary compound of the AlGaAs/GaAs heterojunction. For a n type GaAs diode with L equals 3 micrometers and doped with 1022 m-3, a Al0.3Ga0.7As n layer is predicted to lead to current oscillations of about 30 GHz.

An attempt is made to show the current state of the art in VLSI layout synthesis. This is a very difficult task, because the area is moving very fast. There are also many different design methodologies and styles. We see currently no way to decide which method is the best for what application. An ''ideal'' method is proposed first that covers most of the design tasks and a number of solutions are explained very briefly to provide at least some understanding of the underlying ideas. Also a brief description of the important topic ''framework'' is given. Most of the referenced articles are chosen from 1989 and 1990 conferences.

A logic synthesis package (LSP) is presented in connection with a method for generation of a logic specification from a behavioral description of a digital circuit. LSP is designed to be attached to a silicon compiler, providing a series of primitives which support typical logical synthesis operations like translation into a lower level form, verification, and minimization. The method was applied to the BELA compiler, a FSM (Finite State Machine) synthesizer tool. For the purpose of presentation, the logic synthesis method was divided into two parts. The first part involves synthesis of purely combinational logic. The second part concerns verification, the extraction of a functional form from the input description and involves sequencing. This paper covers the fist part of the synthesis method. A future paper, using the concepts developed here, shall present the second part of the synthesis method.

Software-based circuit simulators had a ten-fold speed improvement in the last 15 years. Despite this they are not fast enough to cost- effectively deal with current VLSI circuits. In this paper we describe the current status of the ABACUS circuit simulator project, which takes advantage of both a dedicated hardware to speed up circuit simulation and a new methodology, where each parallel processor behaves like a circuit element.

This paper presents an algorithm for state assignment in incompletely specified finite state machines, based on a set of heuristic rules. These rules are used to build a desired adjacency graph in which a weight is associated to each possible adjacency. A new method of assigning codes to each state is presented with the goal of choosing adjacencies with large weights.

This paper gives an overview of the principles and hardware realizations of artificial neural networks. The first section describes the operation of neural networks, using simple examples to illustrate some of its key properties. Next the different architectures are described, including single and multiple perceptron networks, Hopfield and Kohonen nets. A brief discussion of the learning rules employed in feedforward and feedback networks follows. The final section discusses hardware implementations of neural systems with emphasis on analog VLSI. Different approaches for the realizations of neurons and synapses are described. A brief comparison between analog and digital techniques is given.

Experimental and algorithmic methods used for extracting electrical model parameters for small geometry MOS transistors are discussed. Results for such methods in micron-sized transistors are shown and SEPE - a PC-based algorithmic extractor using Levenberg-Marquardt algorithm for nonlinear fitting of DC parameters - is described. Its architecture and functions are presented followed by some specific results.

This work intend to provide an overview of some implementation aspects of Design of Testability through Level Sensitive Scan Design (LSSD) Techniques in two different IC designs developed by the IC Design Group at IBM Brasil Hardware Technology Center. Aspects include LSSD Design Methodology, test pin overhead, logic overhead, fault coverage, and test generation effort.

This paper descrIbes the design of the MACONDO1 microprocessor datapath subsystems (16 bits RISC microprocessor): 16 bits ALU, shifter, special purpose registers, fetch machine and a 16 x 16 Reyster bank. These subsystems were implemented using a gate array mat'lx (sea of gates structure) based on the architecture conceived by Van Noije , and adapted to the 2 pm ful I custom technology from the European Silicon Structures (E52). In order the optimize tre gate array2efficiency a basic ccii was designed. An integration of 1270 transistors/mm a good routing flexibility and performance have been achieved. Also, a 2 jim CMOS Gate Array basic I ibrary was developed and electrically characterized. These functIons are required for designing every subsystem. ii, order to establish the relevant features of the main subsystems, a careful analysis of the data flow through the data path was realized. Special attention was given on the aritmetic loyic unit In which was used a transmission gate based logic style. From the simulation results under typical operations conditions, a propagation delay of 35 ns in its most critical path was obtained. As regards the memory cell of the register bank, a careful study of its stability under normal operation conditions was realtzed due to the existency of fixed transistors sizes. A maximum oPeration2frequency of 10 Mhz was observed. The total area of the register bank is 4 mm Finally, through a Multiproject Chip, two chips containing four bit slices of the whole system are being processed at the ES2 SiHcon Foundry (France).

This paper describes a program, EXTRIBO, that extracts NMOS or CMOS circuit netlists from hierarchical layout descriptions, generating hierarchical netlists. EXTRIBO runs on IBM PC compatible computers. It has options to make a transistor only or a detailed extraction including the parasitic resistances and capacitances. This paper is an overview of the program features, explaining the algorithms used.