Metallization, and conductor systems in general, are a critical part of any VLSI chip, and as such can act to set limits on future down-scaling of such integrated circuits. Due to decreasing lateral and vertical dimensions, interconnections are rapidly becoming a problem in terms of device yield, reliability, signal delay time, and inter-device interactions. In this paper, we discuss how interconnection limitations will affect the scaling of advanced circuits. We will also cover a number of issues regarding the interconnection technologies that will be required in future ULSI circuits. The problems with conductor systems begin with the interconnection topology which provides constraints and limitations. The physical problems then begin with the deposition of the materials. For example, chemical vapor deposition of metal or metal-silicide interconnects causes several unique concerns due to surface chemistry, leading to undersirable reactions and compositional and structural nonuniformities. Similarly, factors such as control of step coverage are important for reduced geometries. Recent experiments and modeling techniques which address these problems will therefore be described. Lithographical aspects also pose problems in the scaling of metal lines and new pattern definition techniques will be discussed. Finally, isolation of information within dense crossing interconnects can become very difficult, with coupling causing degradation of information within localized devices.
Multilevel metallization is an indispensable requirement for dense VLSI or ULSI because each additional level can significantly reduce the chip size. Multi-device integration is another trend for higher on-chip performance in which many different device structures, including non-planar trench structures, are fabricated from different material.
Chemical vapor deposition of copper, in hot- and warm-wall reactors from a variety of copper(I)compounds of general formula XCuLn where X = (3-diketonate and 13-ketoiminate and L = phosphine, olefin and alkyne, has been investigated. All compounds deposit high-purity copper, as determined by Auger electron spectroscopy, over the temperature range 100-400°C and pressure range 10 - 150mtorr, with resistivities in the range 1.8 - 5.1 µohmcm. Selective deposition has been studied as a function of theneutral Lewis base ligand, L. The (R-diketonate)Cu(phosphine) compounds have been show to deposit copper selectively onto Pt, W and Cu in the presence of Si02. The temperature range over which selectivity was observed was a function of the substituents on the 13-diketonate ligand. The ([3- diketonate)Cu(1,5-cyclooctadiene) and ([3-diketonate)Cu(alkyne) compounds studied to date did notexhibit selectivity for the above metal substrates over Si02. Deposition rates of up to 9,000Å/min at 200°C have been obtained in a cold-wall CVD reactor under surface reaction limited conditions. Activation energy parameters were measured from the temperature variation of the deposition rate were in the range 21 - 26kcal/mol for (hfac)Cu(PMe3), (hfac)Cu(1,5-cyclooctadiene) and (hfac)Cu(2-butyne). All three classes of compounds undergo a thermally induced disproportionation according to the general reaction shown below.
A low dielectric constant fluorinated polyimide has been employed as the interlevel dielectric in a four-level metal VLSI process. Due to the stringent requirement of a near global planar topography compared with the partial planarizing properties of the polyimide, two advanced approaches were evaluated: (1) a "negative-image" sacrificial photoresist etchback process, and (2) a photoresist image reversal plus dry etch process. Both techniques remove the polyimide from the surface of the metal while leaving polyimide "islands" or "plugs" between the metal features. A second polyimide layer is then applied. The planarity of the finished structure is controlled by the thickness of the initial polyimide layer, the plasma etch process, and the planarizing characteristics of the second or "recoat" polyimide film. The improved global planarity achievable using the advanced techniques were compared to a standard single spin polyimide process using surface profilometer profiles and cross-sectional SEM micrographs. The pros and cons of the two planarization techniques are also discussed.
The local modification of an integrated circuit (IC) requires in general the availability of three generic processes. First, a method for cutting conductors must be provided. Second, a process for depositing new conductors must be available. Finally, a means of opening via holes through the chip passivation to the underlying conductors is needed; this operation enables newly deposited conductors to make connections to the existing circuit elements, and also provides probe access to facilitate testing of the circuit.
This paper briefly reviews techniques to assess and model ohmic contacts between layers with finite conductivity. It is then extended to consider aspects of these models that are applicable to multilayer structures such as those found in high electron mobility transistors [HEMTS] and provides electrical models for these structures. Experimental results are included in some instances to provide insight into the magnitude of the parameters of the models.
There are increasing reliability concerns of electromigration-induced and thermal stress-induced failures in submicron interconnects carrying the projected high current density and in multilevel interconnection with W studs. Electromigration characteristics of Al and Al-Cu submicron lines, two level Al-Cu lines with W studs, Al fine lines under pulsed current stressing at high frequencies, and Al and Al-Cu fine lines under temperature cycling have been systematically studied. Lifetime is affected by grain size, grain morphology and bend structure in submicron metal lines. The lifetime of W stud chains is less than a half of that of Al-Cu flat lines. The discontinuity of Cu supply at Al-Cu/W interfaces account for most of the reduction in the electromigration resistance of W stud chains. Under pulsed current stressing at frequencies 50-200 MHz, our data indicate no threshold frequency for drastic change in lifetime. However, lifetime increases with duty cycle as tso cc r- Z.', which is a remarkable improvement over an av¬ erage current density model. Lifetime also depends explicitly on both current on-time and current off period. The extra thermal stress induced by temperature cycling shortens the lifetime of both Al and Al-Cu fine lines by more than an order of magnitude. Our results also show that the addition of Cu in Al fine lines improves the resistance to thermal stress-induced failures, probably by the suppression of grain boundary sliding and migration.
The distribution of copper in aluminum thin films is examined with respect to how the copper can influence electromigration behavior. Al-Cu thin films annealed in the single phase region, to just below the solvustemperature, have 0-phase Al2Cu precipitates at the aluminum grain boundaries. The grain boundaries between precipitates are depleted in copper. Al-Cu thin films heat treated at lower temperatures, within thetwo phase region, also have 0-phase precipitates at the grain boundaries but the aluminum grain boundariescontinuously become enriched in copper, perhaps due to the formation of a thin coating of 0-phase at the grain boundary. Here, it is proposed that electromigration behavior of aluminum is improved by addingcopper because the 0-phase precipitates may hinder aluminum diffusion along the grain boundaries. It was also found that resistivity of Al-Cu thin films decrease during accelerated electromigration testing prior to failure. Pure Al films did not exhibit this behavior. The decrease in resistivity is attributed to theredistribution of copper from the aluminum grain matrix to the 0-phase precipitates growing at the grain boundaries thereby reducing the number of defects in the microstructure.
Fabrication of microelectronic metal interconnects generates a state of tensile stress in the metal. For constant metal and passivation film thicknesses, the magnitude of stress increases as linewidth decreases until the metal forms internal voids in order to relax. Such voids can grow large enough to sever lines, degrading chip functionality and reliability. For narrow lines, constraints from the passivation layer permit relaxation through void growth to occur only by diffusion. This phenom¬ enon is known as stress migration, by analogy to voiding produced by high electrical current (electromigration). To study the influence of alloy composition and microstructure on diffusion in Al-based interconnects with and without Ti underlayers, interconnects with different amounts of Si, Cu and oxygen were passivated with PECVD SiN, and aged at 150° C for 1000 hr in air. Samples were also electromigration-stressed to highlight possible interactive variables. AI-Cu produces fewer voids and longer electromigration lifetimes than pure Al. High (> 2%) Si appears to promote void formation by rapid grain boundary diffusion and precipitate growth, but does not necessarily decrease electromigration lifetime. Low Si (< 1%) appears to be beneficial for ex¬ tending electromigration lifetime and reducing the total volume of voiding, but causes large void sizes which lead to failure. The effect of oxygen contamination on stress migration is generally detrimental. Ti underlayers are redundant conductors which greatly increase electromigration life, but increase individual void size. A model for thermal dependence of atomic flux, used in con¬ junction with thermal stress hysteresis measurements of metal films, describes a wide range of voiding behavior.
Spin-On Glass (SOG) is used as a planarizing component of the interlevel dielectric in a multilevel integratedcircuit (IC). However, the presence of SOG may compromise IC performance due to water absorption. Several effects will be discussed in the present talk: "Poisoning" of contacts between two metallization levels. Accelerated hot-carrier aging of the MOS transistor.• Formation of mobile positive charge in the SOG layer. The magnitude of this charge may be high enough to invert the silicon surface.• Many-fold increase in the SOG dielectric constant and related increase in parasitic capacitance of the IC.
Electromigration failure in thin film conductors is described. The state of the art in understanding is discussed and the results of new efforts in modeling this important failure mechanism are presented.
Their presently exists a need for an analytical method that can accurately measure both the grain size and thickness of aluminum films deposited under a variety of deposition conditions. In particular, it is especially desirable to be able to make such measurements with high spatial resolution and in a noncontact and nondamaging manner. Using a laser-based thermal wave system with highly focused beams (1 micron spot size) a technique has been developed to satisfy this need. An argon-ion pump beam intensity-modulated in the MHz regime generates thermal waves which are detected via the modulated reflectance of a non-modulated HeNe probe beam. Due to the roughness of the film's surface it is necessary to collect a significant amount of data. Information about the thickness of the film is then based on the average thermal wave signal and grain size information is obtained from the scattering of the thermal wave signal as well as from scattering in the dc reflected argon and HeNe beams. A detailed description of the measurement and the theory behind the analysis will be presented in this talk.
A Focussed Ion beam Microscope has been used to image the grains as well voids formed in Al- 1%Cu/TiW fine line conductors . Void formation has been compared between laser annealed Al and non laser annealed Al and it has been shown that the laser annealed Al is more prone to voiding. A TiW layer placed over the Al is effective in suppressing the voids.
Decohesion of thin films in a multi-level metal IC device is an important reliability concern in semiconductor fabrication. In this study we report measurement of film stress and adhesive bond strength between films used to fabricate a two-level metal VLSI device. The device structure was simulated on Si wafers by sequential deposition of blanket films of LPCVD glass, aluminum, bilayer plasma TEOS interlevel dielectric, and aluminum. Film stress was calculated from wafer bow measurements and adhesive strength was measured using a micro-peel test. Our measurements for all the interfaces showed strong interfacial bonding, greater than the fracture strength of silicon. We also identified that the interface between two layers of plasma TEOS interlevel dielectric can be affected by processing conditions. To insure the robustness of the device structure, the adhesive strength of this interface was studied as a function of various processing parameters. Both individual and cumulative stresses for the device films were measured. The calculated intrinsic peel forces show that spontaneous adhesion failure at the device interfaces is unlikely for optimized processing conditions.