At sub-half micron design rules and smaller, the (multilevel) metallization required to meet performance and reliability requirements are driving the investigation and development of new materials and processing techniques. Step coverage of films in increasingly smaller and deeper structures will mandate fresh approaches in both physical vapor deposition (PVD) and chemical vapor deposition (CVD) film techniques. Low resistivity metals, such as copper, and low permittivity dielectrics, such as polyimide, are being investigated worldwide. Diffusion barrier development has assumed special importance with metallorganic CVD and collimated sputtering PVD techniques showing promise. Key issues are film integrity and density over abrupt topography and effectiveness of the very thin (< 50 nm) layers required for quarter micron via liners. Needs for increased reliability are as much a driver as increased performance. Though copper has been expected to be largely resistant to stress migration effects, recent data have raised doubts. As with all other processes required for deep submicron manufacture, advanced multilevel metallization techniques must conform to increasingly stringent yield criteria and be consistent with requirements of contamination free manufacturing.

Copper, which has a lower electrical resistivity and a higher resistance to electromigration than aluminum, is currently being evaluated for ULSI applications as a replacement for aluminum. Drawbacks to the use of copper include its strong tendency to oxidation, a high mobility in metals and semiconductors, and a high reactivity with silicon at temperatures as low as 200°C. To overcome these problems, very effective diffusion barriers need to be developed. These barriers should have a low diffusivity for copper, a high thermal stability, and should lack a driving force for chemical reactions with Cu, silicon or silicides. Unlike aluminum, copper does not form stable intermetallic compounds with the transition metals of the V and Cr groups, and the mutual solid solubilities of these metals with Cu are low, so that these metals would seem th be a logical choice for barrier applications. It has long been known, however, that these arguments are misleading[1]. Previous studies have indeed shown Cu diffuses through grain boundaries and defects in a tantalum layer and inth silicon at a relatively low temperature (450°C) causing a failure of devices[2,3]. The effectiveness of non-reactive and insoluble tantalum barriers can be improved by adding impurities like oxygen or nitrogen th stuff grain boundaries of the material in order th suppress fast grain boundary diffusion[4]. It is difficult, however to reproducibly improve the effectiveness of barriers by adjusting the level of impurities. Since amorphous alloys lack grain boundaries that can act as fast diffusion paths, they should offer an improved alternative for effective barriers [5-71. In this paper we report on the properties and diffusion barrier performance of amorphous tantalum and tungsten silicides and tantalum-silicon-nitrogen ternary alloys [3,81 for Cu metallizations.

Methods of improving aluminum alloy step coverage, such as high temperature and low power processing, have become well known. Unfortunately, these methods nearly always have drawbacks such as throughput. The process, therefore, needs to be optimized on a case by case basis. An example is provided in this paper for the case of 0.95 micron contacts (1.20 aspect ratio) starting with double level Al-0.5% Cu-1.0% Si with TiN barrier under first level metal and pure Ti under second level metal; 30% step coverage deemed acceptable. Another drawback to standard high temperature Al alloy deposition is the problem of random metal voids. Methods to alleviate this problem are also discussed. Thus there are 2 distinct types of step coverage issues that must be considered separately: (1) inherent step coverage, and (2) random voids. Optimization of each needs to be performed independently.

A four layer metal system, designed for high speed bipolar gate arrays, subjected to high temperature aging was found to contain mechanical stress induced voids at the metal to metal interfaces within micron and sub-micron vias. The interconnect metal used in the system, AlCu(1.5%) sputter deposited at high temperatures, literally fills the vias and is quite resistant to stress voiding in the lines. However, thermal aging at 200 degree(s)C with no current flow led to open circuit failures of the 0.8 micron stacked via structures where via two is place directly over via one, and within via one and via two chains as well. The time to failure was studied as a function of temperature, via dimension, and processing changes to both the surrounding dielectric and the metallization. Reliability studies of the original, unmodified via structure, as well as those with process changes as indicated above have identified some of the significant factors affecting stress controlled via reliability.

The electromigration behavior of Ti-AlCu-Ti metallurgy is presented in this work. For single- level structures in the absence of tungsten (W) stud interconnections, a greater-than-100X lifetime improvement over AlCu is measured. The metal linewidth strongly affects the median time to failure, T₅₀, and standard deviation, sigma ((sigma) ), of the lognormal distribution. For two-level W stud chains, a 50X degradation in lifetime as compared to single-level structures is measured. The lifetime of these W stud chains depends on the Ti- AlCu-Ti current density rather than the stud current density. The 'reservoir effect', in which the electromigration lifetime of Ti-AlCu-Ti stripes depends strongly on W studs near the electron source end of the stripes, is a direct result of W acting as a diffusion barrier. The lifetime of W stud chains with Ti-AlCu-Ti metallurgy is longer for 2.0% copper than for 0.5% copper.

The electromigration resistance for Al-Cu-Si alloy over a Ti underlayer as a function of the initial Ti thickness in the range of 0 angstroms - 1000 angstroms is investigated. After the Ti deposition, test structures have been divided into groups with and without a rapid thermal anneal (RTA) in an ammonia ambient to form a TiN barrier. The electromigration resistance of these barrier metallization systems, in general, increases with the initial Ti thickness, except when the initial Ti thickness is less than 600 angstroms for the RTA TiN/Al-Cu-Si system. A model is proposed to explain this electromigration characteristic as a function of the initial Ti thickness for these barrier metallization systems, with the support of texture analysis of the Al-alloy surface and stress measurements of barrier layers using X-ray diffraction and wafer curvature. This study highlights a direction of how a Ti-based barrier metallization system should be processed in order to optimize its electromigration resistance.

The role of microstructure is becoming increasingly important as minimum feature sizes decrease in succeeding generations of devices. To insure reliability, advances have been made in aluminum-based interconnects in the form of new metallurgies and multilayer metal structures. The interplay of metallurgy and microstructure now must be understood in lines with widths less than 0.5 micrometers . This paper will analyze the texture effects on electromigration behavior in pure Al, AlCu, and multilayer Ti/AlCu/Ti metallurgies being mindful that the texture is inseparable from other aspects of microstructure such as grain size and grain size distribution. An increasingly strong (111) textures shows higher mean time to failure and lower dispersion. Preliminary results indicate that narrow line widths produce higher dispersion of failure times regardless of the texture. The texture depends on deposition conditions, annealing conditions, and type of substrate (amorphous or oriented crystalline) whereas alloy content alone has not been found to have a measurable effect on the texture. In general, sputtered textures are sharper (lower spread of the (111) fiber distribution) than evaporated textures. Annealing at temperatures sufficiently high to induce grain growth sharpens the (111) texture and/or decreases the fraction of randomly oriented grains. Finally, deposition on a thin, highly textured titanium underlayer sharpens the subsequent aluminum alloy texture.

Electromigration (EM) phenomena are generally and quite accurately attributed to electron flow enhanced grain boundary diffusion processes. However, there is clear evidence in the literature and in the work that will be presented, that surface or interface diffusion phenomena also contribute to electromigration damage (EMD) in Al, Cu, and alloy films. Most of this evidence comes from transmission and scanning electron microscope experiments carried out on samples that have experienced the latter stages of EMD stressing. Evidence for surface or interface diffusion occurs in hillock formation and annealing, film thinning, voiding and island formation, and regrowth-healing events on current reversal. The implications of these results in attempting to reduce EMD in microelectronic metallizations are presented.

The effect of strain on grain-boundary diffusion has been evaluated by molecular dynamics simulations. The system studied was a tilt boundary in a fcc bicrystal model with interatomic potential calculated by the Embedded Atom Method. The results confirm the dominance of vacancy jump mechanism in grain-boundary diffusion even with up to 1.0% dilation strain at elevated temperatures. Vacancy jumps confine mostly to within the grain-boundary core. The jump direction is preferentially along the tilt axis. The simulations have yielded, as functions of strain, reasonable values of vacancy formation and migration energies. The relation between diffusivity and atomic mean-square displacement has also been examined and used to calculate grain-boundary diffusivity.

This paper summarizes several different types of current induced (excess) noise time domain waveforms and the power spectra behavior associated with specific ULSI/VLSI interconnection problems. Importance of maintaining waveform stationarity when using 1/f² noise to detect electromigration is illustrated. In addition, non-stationary waveforms, associated with thin films with high degrees of stress are reported. A discussion of large magnitude 1/f spectra associated with the presence of film voids, poor step coverage and/or wire bonding problems is presented.

The properties of spin-on titanium-nitride (SO-TiN) thin films were optimized for integrated- circuit application. The two steps of the spin-on process were characterized: one, the initial step in which a thin-film titanium oxide is formed, and two, the conversion of the thin film to titanium-nitride (TiN) by rapid thermal processing in ammonia. The spin-on TiN showed a uniform coating on a flat wafer surface for all the precursors. However, on non-planar topography some solutions produced cracked films while others did not. The precursor's effect was investigated, and it is proposed that the optimized precursor should include more carbon in the initial annealing stage so the film does not crack. The chosen precursor, titanium- tertiary-butoxide, was investigated and characterized versus processing temperature, heating rate, and gas flow. The experiment was designed at the 700 degree(s)C - 1000 degree(s)C temperature range, with 0.1 - 200 degree(s)C/sec. heating rate, and hold time of 30 - 300 sec. at the upper temperature before rapid cool down. The optimal processing conditions at NH₃ are heating at 100 - 120 degree(s)C/sec. ramp from room temperature up to 900 degree(s)C - 1000 degree(s)C where the wafer is annealed for 30 - 100 seconds before rapid cool down to room temperature.

We report here a new, noncontacting, and nondestructive photothermal phase microscope to measure metal film thickness in integrated circuit devices down to 150 angstroms with a 30 angstroms sensitivity. A thermal diffusion wave ranging from 3 - 500 MHz is excited with an intensity modulated laser beam. The wave is reflected by the insulating layer underneath the metal film back to the surface. A second laser beam measures the reflected thermal wave using the fact that the surface reflectance is a function of the temperature. The phase delay between the surface temperature variation and the heating beam modulation yields the thickness of the opaque film. Since the technique uses the phase of the photothermal signal, instead of amplitude, the result is not critically dependent on the surface roughness or tilt of the sample. In addition, the measurement can work with very small pads (3 micrometers X 3 micrometers ).

A highly reliable high-temperature Al-Si-Cu sputter metallization, employing a Ti underlayer to prevent Si from precipitating has been developed, and complete filling of 0.15 micrometers diameter vias with aspect ratio of 4.5 has been achieved. Degree of filling and via chain resistance were improved by increasing the Ti underlayer thickness. This is probably because of improvement in wettability of Al on via sidewall, which is caused by uniform interfacial reaction between Ti underlayers and Al-Si-Cu films. Transmission electron microscopy (TEM) combined with micro energy dispersive spectrometry (EDS) analysis revealed that reacted ball-like precipitates exist at the interface between the first metal and the second metal lines in the filled via, and that the precipitates particles are Al-Ti-Si compounds. No Si precipitation was observed in areas away from or near to the particles. Also, it was found that Al films in the vias consist of one or two single crystalline <111> textured normal to a substrate. The electrical resistance for the 0.3 micrometers sputter filled via was 0.71 (Omega) , which is about one order of magnitude lower than that for a non-filled (conventional) via. The electromigration (EM) resistance of 0.3 micrometers filled vias was found to be four orders of magnitude greater than that for the 0.3 micrometers conventional vias. Furthermore, we confirmed that the EM resistance for the 0.3 micrometers filled via is comparable to the 0.9 micrometers conventional via. Superior EM and stress-induced migration (SM) resistance for the lines have been confirmed.

The techniques to study signal delay distortion and crosstalk in high density VLSI/ULSI micron and submicron interconnects are reviewed. These include numerical techniques based on the method of characteristics and the transform based techniques as well as frequency and time domain measurement techniques. The limitations of the classical modeling and measurement techniques in the submicron metallization regime are examined.

This paper discusses techniques with metal melting by laser irradiation for via hole filling and planarization of the metal film. In the planarization of metal film, a pure Al film has been melted by one optical pulse irradiation from an ArF excimer laser, resulting in realization of the planarization and via hole filling. A technique for producing metal plugs has been developed for via hole filling. In this technique, a thin metal film is patterned to be covering the entire via hole. The patterning controls the total amount of metal which is filled in the via hole. A metal cap is fabricated by this patterning, followed by melting with a XeCl excimer laser irradiation. The molten metal cap is drawn to the via during the mass transport procedure, resulting in formation of the metal plug. The mass transport mechanism of molten metal has been cleared up. The mass transport for the plug formation is attributed to the surface tension forces created by the three-dimensional geometry of the molten metal. The use of metal cap brings that the plug formation is performed easily and stably. And further, this technique is an effective method for submicron interconnection. The interconnects on contact check device are improved by the plug formation. The contact check device is composed of 60000 vias connected in series. These characteristics agree well with the results calculated using electrical resistivity of metal.

Smart-power technologies that provide on-chip integration of power and signal devices offer a unique challenge in process integration. Metallization plays a pivotal role as it critically impacts the performance and reliability of both the signal and power devices. This talk will address the most critical issues pertaining to device performance/reliability and process integration of smart-power technologies based on the experimental data obtained from a variety of metallization systems including TiSi₂, LPCVD tungsten, and LPCVD WSi₂. The talk will identify the important challenges and opportunities for further work in this technologically vital area.

Analytical expressions for the sensitivities of the S-parameters of a MESFET are presented. These expressions are useful for optimizing the gate and source metallization resistances for design of MESFETs. The final expressions are given in terms of general circuit impedances and therefore can be used in analyzing other solid state three terminal active devices.

By using the low kinetic energy particle process, Cu films grown on SiO₂ under a sufficient amount of energy deposition exhibit almost perfect crystal orientation conversion from Cu(111) to Cu(100) after thermal annealing. This crystal orientation conversion is always accompanied by giant-grain-growth in the film as large as several hundred micrometers. The crystal orientation conversion is primarily governed by the total energy density deposited to the film during film growth. In this work, we have discovered another important factor that governs the crystal orientation conversion, i.e., the total amount of energy deposition to the entire film. The crystal orientation conversion by thermal annealing is observed only for film thickness greater than 1.0 micrometers . In terms of electrical properties, the resistivity of giant- grain-Cu film at a room temperature is 1.78 (mu) (Omega) (DOT)cm, which is almost identical to the bulk resistivity (1.72 (mu) (Omega) (DOT)cm). And electromigration lifetime for giant- grain-Cu interconnect is approximately 3 - 5 orders of magnitude larger than those for Al-alloy interconnects at a room temperature.

Amorphous carbon films have been deposited by plasma enhanced chemical vapor deposition which provide a high degree of planarization over large distances. These films can be deposited at room temperature with low ion bombardment energy (10 V) and high deposition rate (300 nm/min). The planar films have low viscosity and molecular weight, and their molecular structure is similar to that of the source gases. A post-deposition hardening step was utilized to improve the compatibility of the films with subsequent processing steps by heating the samples and/or exposing them to a low power plasma. Submicrometer patterns have been defined using excimer laser projection lithography in bilayer resist. In addition, a multipolar electron cyclotron resonance source was used to generate an oxygen plasma for Si oxidation. Oxidation rate was found to increase with microwave power but decrease with source distance and rf power. Maximum oxidation rate was found at 0.25 mTorr. This low pressure is desirable for forming conformal insulator. The oxide films were found to have O to Si ratio of 2 and refractive index of 1.47. Breakdown field was >12 MV/cm and fixed charge density was 3 X 10¹⁰ cm^-2.

Planarization, conformal coating and etch selectivity are three key areas for successful fabrication of submicron interconnections, BCl₃ and BCl₃/N₂ RIE (Reactive Ion Etch) are usually used to define high aspect ratio and fine edge submicron Al lines. Polymers have potential for being used as the insulator for multilevel interconnections, because of their low dielectric constants. Due to viscosity, it is difficult to coat the space between submicron metal lines with spin on formulations for polymers. Parylene is a family of conformal vapor depositable polymers with many attractive attributes, such as low dielectric constant (2.38 - 2.65), no outgassing or moisture uptake, room temperature deposition, low stress, good gap filling and local planarization properties. However, with this 'new' polymer insulator, selectivity becomes important for proper etch stop. In this paper the RIE etch selectivities of Al and parylene have been investigated and the selectivity explored to pattern micron feature size interconnections. The Al was deposited on parylene and patterned for studying etch selectivity. The planarization capability of parylene was also studied. It is demonstrated that high aspect ratio sub-micron trenches could be successfully conformally coated with parylene. The metal-polymer adhesion and diffusion characteristics are also examined; and low mechanical stress for the dielectric are demonstrated.

Issues of interconnection technologies for quarter-micron devices are the reliability of metal lines with quarter-micron feature sizes and the formation of contact-hole-plugs with high aspect ratios. This paper describes a TiN/Al-Si-Cu/TiN/Al-Si-Cu/TiN/Ti multilayer conductor structure as a quarter-micron interconnection technology and aluminum-germanium (Al-Ge) reflow sputtering as a contact-hole filling technology. The TiN/Al-Si-Cu/TiN/Al-Si-Cu/TiN/Ti multilayer conductor structure could suppress stress-induced voiding and improve the electromigration mean-time to failure. These improvements are attributed to the fact that the grain boundaries for the Al-Si-Cu film and the interfaces between the Al-Si-Cu and the TiN films are strengthened by the rigid intermetallic compound, TiAl₃. The Al-Ge alloy reflow sputtering is a candidate for contact- and via-hole filling technologies in terms of reducing fabrication costs. The Al-Ge reflow sputtering achieved low temperature contact hole filling at 300 degree(s)C. Contact holes with a diameter of 0.25 micrometers and aspect ratio of 4 could be filled. This is attributed to the low eutectic temperature for Al-Ge (424 degree(s)C) and the effect of thin polysilicon underlayer on the enhancement of Al-Ge reflow.

Consistently low contact resistance is critical to performance and reliability of CMOS devices. Shrinking cell sizes have driven contact dimensions to increasingly higher aspect ratios. Previous technologies have used conventionally sputtered Ti/TiN contact liner films to provide good metallurgical bonding and electrical conductivity between silicide—clad diffusions and tungsten contact studs. However, for high aspect-ratio contacts, step coverage of conventional PVD Ti may not be adequate. It has bcen shown that step coverage may be enhanced through the use of a collimator. A collimator is a honeycomb-like device suspended between the target and wafer. This device screens sputtered species which travel in paths with angles of incidence non-normal to the wafer surface. This paper describes the development and evaluation of a 200 mm collimated titanium process for the IBM 16 Mb-DRAM. The 16-Mb device employs TiSi2-clad diffusions which are passivated with a doped glass. Contacts are patterned and etched through the glass to open the diffusions. The contact dimensions are nominally O.6-m in diameter by 1 .2-sm deep. Following etching, a Ti/TiN bilayer is deposited onto the wafer and CVD tungsten is deposited and planarized to form the contact stud. In the 16-Mb development program Ti coverage of the bottom of the contact was found to be critical to a robust process. Titanium is known to be highly reactive and is thought to consume native oxides and RIE residuals on the suicide surface. For contact dimensions currently under consideration, step coverage of conventional PVD films was typically < 10% . Step coverage of 15-40% has been demonstrated with collimation. Comparison of contact resistance data from wafers processed with collimated and conventionally deposited liner films shows a profound improvement with coffimation. Mean contact resistance for wafers with the conventional PVD liner process is typically greater than 100 ohms, with collimation, the resistance is typically less than 5 ohms. The presentation will also summarize a large database that has been generated on process stability, collimator lifetime and particulate performance.

Although rapid thermal processing (RTP) has existed for a number of years, difficulties associated with pyrometric temperature measurement and control have prevented RTP's widespread acceptance in manufacturing. We show that nominal process-associated film thickness variations drastically reduce the wafer-to-wafer process repeatability using pyrometry. These thickness variations lead to large changes in wafer emissivity producing temperature errors of as much as +/- 100 K. The result is reduced process capability which limits the utility of RTP in manufacturing. This paper contrasts pyrometric temperature feedback with power control (PC). The data indicate that PC results in significant reduction of wafer-to-wafer temperature fluctuations, to better than +/- 5 K. The improvement is due to minimal sensitivity of PC to dielectric-film-induced wafer emissivity fluctuations. Therefore, PC can be used without the need for back-side strip, allowing seamless integration into semiconductor processing. We also present a theoretical basis for power control and discuss the limitations and boundary conditions governing the technique.

As wiring interconnects evolve toward submicron and multilayered structures, electromigration and stress-induced failures become increasingly important for device yield and reliability. This paper discusses the present understanding of these reliability problems in multilevel interconnects formed with Al-based metallization. The multilevel structure and the submicron dimension alter the nature of the flux divergence, increasing the role of stud and interface in controlling damage formation. These effects are illustrated using the results of a recent study on electromigration failure in an advanced Al(Cu)/W two-level line/stud structure. To understand the mechanism for stress-induced void formation, the characteristics of thermal stress and stress relaxation in confined line structures are discussed. The confinement by the dielectric layer and the narrow width of the line are important factors in raising the stress level to cause void formation. Stress relaxation controls the kinetics of void growth and its mechanism is discussed.

The reliability of the narrow, passivated metal lines connecting devices in microelectronic circuits may well define an ultimate limit for achievable device density and circuit performance. Rather than average lifetimes, we are usually concerned with the first failures among millions of lines. The extrapolation of a limited number of accelerated test results to service conditions and very early failure clearly requires a fundamental understanding of the possible failure mechanisms. Based on recent theoretical progress we discuss current and potential capabilities in the modelling of failure distributions. In general, electromigration induced failure distributions can be calculated, if the detailed distributions of microstructure, precipitates and thermal stress induced voids are known.

Stress-induced voiding of 1.2 micrometers wide metal 1 lines is quantified for two different interlevel dielectric schemes. The first involves a multi-step sequence of PETEOS depositions and etchbacks. The second is a PETEOS/siloxane spin-on-glass/PETEOS sandwich. Metal 1 consists of 4500 angstroms of Al (0.75% Si, 0.5% Cu) over 600 angstroms of Ti/TiN. Separate experiments show the stresses in the PETEOS and SOG films are compressive and tensile, respectively. After 2000 hr. at 175 degree(s)C, metal 1 lines covered by the spin-on- glass sandwich dielectric exhibit considerably fewer voids that penetrate <EQ 30% of linewidth and a comparably low density of voids that penetrate 30 - 50% of linewidth. No voids > 50% of linewidth are observed with either dielectric scheme. This result indicates that the spin-on glass is able to reduce the net voiding stresses in the aluminum.

Stress-induced void growth is modeled for the case of a void bounded by two neighbors by invoking the one-dimensional diffusion equation. The resultant equation is then convoluted with an exponential distribution for void spacing to generate the mean void size as a function of time. Volumetric strain, atomic diffusivity and activation energy are then extracted for a given metallization and passivation system by fitting measured mean void size data to the analytical curve.

Electromigration lifetime under DC current stress is now routinely measured to support new metallization process development as well as to monitor the control of an existing process. The measured DC lifetime value, or design rule, is the only link between process technology and circuit design for metal reliability. This paper reviews a defect relaxation model for pulsed DC (non-alternating) current stress lifetime and a damage-healing model for AC (bidirectional) current stress lifetime. The purpose is to model the metal reliability of IC's. Both models significantly raise the predicted lifetime beyond the predictions of some previous models.

Electromigration performance is investigated for Al-Si(1%)-Cu(0.5%) alloy on a CVD-W or Ti:W barrier layer, and the effectiveness of a Ti:W capping layer to suppress electromigration is explored. Compared to a Ti:W barrier layer, the surface roughness of the CVD-W barrier layer degrades electromigration performance, however, a capping layer of Ti:W sequentially sputtered on top of the aluminum-alloy will substantively improve the electromigration performance when either barrier layer system is used. The improvement is observed to increase with the thickness of the Ti:W capping layer. Investigations of the failure kinetics and material properties indicate the EM performance improvement is primarily due to changes in the Al-alloy micro-structure.

Microstructural and crystallographic characterizations of electromigration induced voiding and damage in Al and Al-2% Cu interconnects are presented. Scanning electron and focussed ion beam micrographs show that extended voiding in wide lines and transgranular slit voids in near bamboo lines are the preferred failure morphologies. Electron back scattered diffraction analysis of transgranular slit failure sites show a preferred <110> slit void orientation. Estimates of stresses required for stress assisted void growth in unpassivated interconnects are shown to be reasonably close to measured stress levels in films and interconnects. The transgranular void process is shown to be preferred over boundary voiding based on usual estimates for the variation of surface energy and random boundary energies in Al. Finally, line edge void growth into transgranular slit failures at favorably stressed and crystallographically oriented grain sites is presented as an empirical model for the observed electromigration induced failures in near bamboo interconnects lines.

The trend of the performance degradations, noise and reliability issues and their potential solutions are analyzed for the submicron ULSI interconnect lines. To analyze these submicron interconnect lines, a new paradigm (HIVE) for fast and accurate 2-D and 3-D interconnect capacitances and resistances calculation is developed. The analysis, using these interconnect parameters for HIVE, shows that a copper (Cu) line will improve the electromigrations, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improve the interconnect delay and electromigration, but it increases the cost of system packaging. The optimum approach will be the combination of additional layers of non-scaled metal lines in a higher level, low permittivity interlevel dielectric, and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.

Effects of long wire RC delay to circuit and system performance are investigated for sub- micron on-chip interconnections corresponding to 0.75 to 0.25 micrometers CMOS technologies. A system performance model based on hypothetic microprocessors, projected from previous generations, is introduced for the performance analysis. From the analysis, it is found that non-scaled upper wiring levels (wide wires) for long global interconnections is the most effective approach to improve system performance with sub-micron-pitch interconnections. It can provide 70% performance improvement over the wide wire approach, which increase only wire width for long interconnections. The fat wire approach, however, requires some technology modifications, as well as one more wiring level than conventional approaches.

Attempts to improve the reliability of narrow passivated Al/Cu conductors as defined by the performance in an accelerated electromigration test are reviewed. The results are explained in terms of the effect of thermally induced stress and stress voiding on electromigration lifetime. Other processing variations which produced small or inconsequential changes are also discussed. In addition, it was observed that electromigration performance in samples susceptible to stress voiding was degraded as a function of storage time at room temperature.

The multilevel interconnect to be investigated consist of a first level aluminum line (M1) connected to a second level aluminum line (M2) by a tungsten via-stud (S1). In the manufacturing process, thermal voiding is often observed in passivated aluminum lines near the via-stud. The purpose of this work is to calculate the thermal stresses in a typical passivated multilevel metal-stud-metal structure using the finite element method. Variations of stresses with the tungsten via-stud intersect area, height, and its alignment with respect to M1 have been considered. It is shown that the local stresses in the aluminum line (M1) increase by 25%, the maxima located under the tungsten via-stud. The stresses further increase if the via- stud is misaligned to abut the end of the line. The average stress in the line is not significantly influenced by variation in stud dimensions of 30% about the nominal case, indicating that the stress response is dominated by the passivation. Higher stresses are calculated for SiN_x passivation as compared to SiO₂ since the former is twice as stiff.

Chemical Mechanical Polishing (CMP) is becoming a mainstream technology for the planarization of dielectrics at various process levels. Widely different types of glass films are now routinely processed using CMP techniques. In this work, the polish rates using an aqueous silica based slurry for thermally grown SiO₂, plasma deposited SiO₂, and boro-phospho-silicate glasses have been compared. A polishing mechanism based on the concentration of water in the glass is proposed. It is also shown that the presence of phosphorous changes the polishing mechanism compared to undoped glasses and the rate increase due to phosphorous is much greater than that due to boron.