In this paper a triple level metal interconnect process for a commercially available high density, high performance 0.6 micrometers /5V CMOS technology is described. Poly gates of 0.6 micrometers (L_eff equals 0.45 micrometers ) were fabricated and then planarized by BPSG reflow and resist etch back. Blanket W and etch back were used to fill high aspect ratio contacts and vias with TiN as the nucleation barrier. Low temperature RTA was performed after Ti/TiN deposition, and rf etch was performed for contacts and vias respectively, prior to Ti/TiN depositing, to achieve reliable contacts and via resistance. Stable contacts/via resistance down to 0.7 micrometers with good junction integrity/stackability and negative metal enclosure have been demonstrated and been physically characterized by HTEM. TiN/Al-Cu/TiN was used for M1/M2/M3 interconnection and TEOS/resist etch back/TEOS refill was used for ILD1 and ILD2. A TEOS/nitride sandwich was used for final passivation. A satisfactory yield has been achieved on 2.9 cm² die size with 0.6 million usable gates.

TiN films were sputtered deposited through a collimating medium under different conditions where the sputter target was maintained in nitrided and non-nitrided modes. In-situ rapid thermal (RTP) annealing was done in an applied materials metal anneal chamber (MAC) integrated with the Endura physical vapor deposition (PVD) system. The barrier properties of these films were evaluated for tungsten plug application. Contact resistances and junction leakage data are presented. It is seen that the TiN films deposited in the non-nitrided mode possess excellent barrier properties. This method of deposition offers significantly improved wafer throughputs for coherent sputtering of TiN. The MAC offers an excellent alternative to the conventional furnace annealing approach for contact silicidation and provides a means for improving productivity.

In this paper, various multilayer metallization schemes for 0.5 micrometers CMOS technology are studied. Experimental results show that multilayer interconnect consisting of AlCu on Ti/TiN barrier layer has superior electromigration resistance as compared to that deposited on single TiN film. The application of an advanced wafer-level reliability test enables us to investigate grain boundary diffusion controlled electromigration phenomenon. The microstructural properties of the metallizations are also characterized by x-ray diffraction and scanning electron microscope. The stress migration resistance is also studied using high temperature storage at 175 degree(s)C and thermal cycle treatment at 450 degree(s)C.

Deep sub micron high aspect ratio contacts used for ULSI require highly conformal Ti and TiN films for W contact plug technology. Collimated Ti sputtering has been shown to enhance the coverage of Ti at the bottom of the contacts which helps obtain low contact resistance. However, insufficient sidewall and bottom corner coverage results in failure of the TiN barrier during subsequent processing. Conformal CVD TiN with collimated Ti is proposed as a technology of choice for obtaining low resistance and highly reliable contacts for advanced ULSI applications.

The relationship between photoresist treatment prior to etch and subsequent oxide sidewall hole profile is investigated. Etched features were examined immediately after resist pattern definition with post-expose bake, then after oven hard bake or deep UV photostabilization. It was observed that taper of the etched oxide profile depends on pre-treatment temperature. Etch chemistry influences the relative change in taper across a range of pre-treatment temperatures. `Bowing,' as well as reticulated or `burnt' resist is eliminated. Profile variation across the wafer is reduced with deep UV photostabilization. Microscopic etch uniformity (RIE lag) also depends on the interaction between resist pre-treatment and oxide etch chemistry.

The interaction of ILD (interlevel dielectric) thickness with slope etch depth on the performance of single and stacked vias has been characterized on a four-layer metal high performance bipolar device. Both wet and dry slope etches, which have significantly different cross sectional profiles, were investigated. As expected, the aspect ratio (AR) of the vertical wall of the via was critical in determining how well the via filled with hot Al/Cu: at AR > 0.8, some open vias were observed. However, it was also found that excessive dry slope etch could cause via performance to degrade. For a given ILD thickness, increasing the depth of the dry slope etch could cause via resistance to increase. In addition, for a constant RIE time (varied ILD thickness), deeper slope etches resulted in higher via resistance. These results are discussed in terms of an interaction between the dry slope etch and the amount of RIE overetch time.

We have studied the microstructure, surface roughness, conformality and adhesion properties of chemical vapor deposited copper films using (hfac)Cu(VTMS) in an effort to identify and address some of these issues. The microstructure and surface roughness of the deposited films were evaluated using scanning electron microscopy and atomic force microscopy. The film microstructure changed from columnar oriented faceted grains to finer and more equiaxed grains while the film roughness increased as precursor partial pressure was increased in the reactor chamber. Conformal films were deposited into trenches with sub-half micron openings and aspect ratios greater than 1. The adhesion of CVD copper films on titanium nitride (TiN) and tungsten (W) was also evaluated. The results from this study demonstrate the applicability of CVD copper for ULSI.

In this work an inter-metal dielectric (IMD) planarization process, developed for multimetal submicron technology devices, is presented. The feasibility to build up to five metal levels with W blanket-etch back stacked plug interconnections is shown, using a new Spin On Glass (SOG) material and a semi-integrated planarization process in which a bake, a SOG Partial Etch Back (PEB), and a TEOS oxide cap layer deposition are done sequentially in the same cluster tool. The presented planarization process allows a very low over-etch for the W etch back step at each plug level and, consequently, a quite good control of the plug recession as required by stacked vias. This new process has effectively extended the life of an existing SOG Partial Etch Back process already established on existing equipment. Planarization process performances have been tested on an advanced triple metal device with stacked W plugs and on a test device with five metal levels with various metal pitches. Process results are presented in terms of defect density, repeatability, and electrical tests on stacked via chain structures.

Wafer fabrication technology is rapidly advancing toward three or four layers of metalization with geometry of 0.35 micrometers and smaller, with aspect ratios of 3:1, and a requirement that the interlayer dielectric be globally planarized. Electron cyclotron resonance chemical vapor deposition (ECR CVD) meets the prerequisites for the deposition of SiO₂ in these stringent conditions. Gap fill has been demonstrated on structures of 3:1 aspect ratio and 0.25 mm gap width. The oxide profile resulting from the ECR deposition is also well suited to global planarization by chemical-mechanical polishing (CMP). This paper examines the interaction between these two processes in developing a two step deposition process that achieves the desired film properties as well as providing for the CMP requirements. In step one, the metalization structure is filled with a high sputter etch to deposition rate ratio and then, step two, the ratio is reduced to produce a high deposition rate for the `sacrificial' layer that is polished by CMP.

This work demonstrates the extendability of a resist etch back (REB) planarization technique for use with 0.5 micrometers logic technologies. This new technique compensates for loading effects during etch back. It provides sufficient local and regional planarity for fine line patterning with i-line resists. The new REB planarization is characterized in terms of oxide thicknesses over packed and isolated lines and step heights over packed and isolated spaces. Results of the new process are compared to those of chemical-mechanical polishing in terms of metal serpentine resistances and shorts between interdigitated metal combs. The new process was integrated with collimated sputtered titanium and CVD tungsten providing high aspect ratio contacts and vias with low resistances. Sufficient photolithographic margins were obtained with REB. Together these processes meet the requirements for 0.5 micrometers logic integrated circuits with stacked vias and contacts with up to four levels of metal.

Chemical mechanical polishing (CMP) has emerged as the favored technique for meeting the global planarity requirements of sub-half micron technology. Typically, the slurry used to polish oxide films consists of fine (< 0.5 micron) silica particles dispersed in an alkaline medium such as hydroxides of potassium or ammonia. However, past work on polishing of bulk glass has revealed that compared to silica, oxides of metals such as cerium and aluminum are more chemically active and make more efficient polishing compounds. In this work, we have compared polishing characteristics of oxide films using silica, ceria and alumina slurries. Transmission electron microscopy (TEM) has been used to characterize these different slurries. In addition, the films polished using these slurries have been characterized using various techniques. Consistent with their increased chemical reactivity, ceria based slurries result in increased removal rates for polishing of blanket oxide films. Polishing characteristics of alumina based slurries appear to be a strong function of essential slurry additives.

A SOG/etch-back process has been developed in order to be compatible with a 0.5 micrometers triple level metal technology with plugged vias. Four SOG are compared in terms of planarization level after coating but also after etch-back. The etching process is studied in order to reach the low selectivities required to compensate the microloading effects of patterned wafers. The compromise between high planarization level and low surface roughness is obtained by adjusting selectivity and etching time. Planarization level and complete SOG consumption, required to avoid vias poisoning, can be controlled by measuring TEOS1 consumption after etch-back. Vias and metal yield are measured on different topographies. Results illustrate the planarization efficiency.

Basic film and process characteristics in conjunction with electrical test results are presented showing the effect of implementing a void free oxide for both intermetal and shallow trench isolation. An integrated intermetal dielectric (IMD) process is evaluated on fully functional 0.5 micrometers BiCMOS memory circuits. The integrated process uses two different films, an oxide for gap fill deposited at atmospheric pressure (APCVD) using a TEOS/O₃ chemistry, and a second oxide deposited from TEOS using plasma enhanced CVD(PETEOS) for planarization, stress management, and moisture protection. The effect of a thin PETEOS barrier between TEOS/O₃ and the underlying metal is explored, and some issues concerning the integration of chemical mechanical polishing into a void free backend process flow are investigated. The suitability of undoped APCVD TEOS/O₃ thin films for isolation trench fill is also characterized and described. Process variable which determine the relevant properties for trench fill are evaluated. Well-behaved MOS transistors with excellent parasitic performance were achieved using trench isolation and are reported.

The effect of oxide confinement on the stress and yield behavior of AlCuSi and AlCu films on oxidized Si substrates have been measured by bending beam techniques and examined using a film strength model. Our results reveal that the oxide thickness, alloy thickness, and metal grain size play a role in determining the plastic deformation behavior of the metal films above approximately 200 degree(s)C. The stress analysis of multilayers for bending beam measurements has been extended to include plastic deformation, making it possible to directly determine the effects of the oxide overlayer on the stress and yield behavior of the Al alloy film. Complementary transmission electron microscopy (TEM) studies of the Al alloy reveal that differences in the grain size with and without a SiO₂ passivation layer are central to determining whether an increase in film strength due to the passivation oxide will be observable. The overall experimental results, particularly the contrasting effects observed for AlCuSi and AlCu films, can be satisfactorily accounted for by a film strength model which takes into account the roles of film thickness, oxide thickness, and grain size in controlling the yield strength.

Multilevel metal (MLM) structures utilizing four layers of large grain size Al 1.5% Cu metallization have displayed `in process' stress voiding in metal layers two through four upon completion of final passivation and anneal. Changing the deposited dielectric stress from 2E8 dynes/cm<sup>2</sup> to a slightly more compressive 1.25E9 dynes/cm<sup>2</sup> eliminated the formation of `in process' stress voids. However, thermal stressing at 200 degree(s)C still produced stress voiding in metal layers two and three. The addition of a 125 angstrom TiW cap to the second, third, and fourth metal layer was shown to eliminate both `in process' stress voids and long term 200 degree(s)C thermal stress induced metal line voids on all material with standard dielectric thicknesses. The results comparing various dielectric stress levels and metal structures with and without a TiW cap are reported here.

Vertical links have been processed by application of Q-switched Nd:YAG and Excimer Laser pulses. Investigations were carried out on three different standard CMOS double level metallizations (LS1-LS3). Experimental yield Y_R, contact resistance R_K, their mean R_m and related standard deviations (sigma) _R were obtained from special test structures: contact interconnect (CI) system connected by probe pads and CBKR chains. Simple expanded interconnections of sizes 10 X 10 micrometers ² (10²), 14², and 20² (LS3: 9.6², 12.6², and 19.5²) turned out to be best suitable. In yield evaluation, R_K > 3(Omega) was treated as a failure. Nd:YAG processing gave 100% Y_R for 14², 20², and 19.5² antifuses. Excimer laser processing of LS2 resulted in 100% Y_R for 14² and 20² antifuses, 12.6²-antifuses of LS3 could be connected with Y_R of 99.5%. Conventional accelerated life time tests were carried out on contact chains of LS1 and LS3. For LS3, E_A and n were determined with TRACE.

The primary cause of disc drive failures continues to be component failure of integrated circuits (ICs). A solution to the dilemma is proposed, which is described here as `statistical reliability control' (SRC). After reviewing some limitations and opportunities with the alternatives, this paper focuses on wafer level reliability (WLR) and its potential for being the most statistically significant and cost-effective way to achieve SRC `upstream,' in the IC manufacturing process. This paper briefly discusses WLR's potential as the best vehicle for studying IC failure mechanism kinetics and the relationship of critical process parameters to IC reliability, to help accelerate development of advanced wafer processes and IC packages with built-in reliability. Finally, some comments on Seagate's SRC specification and ideas for implementation and use of this type of spec by users and IC manufacturers are proposed, with the goal of at least reducing many traditional `end-of-line' reliability tests and screens that are sometimes overemphasized, at the expense of directing efforts upstream, where early detection can have the greatest impact on payback and effectiveness.

How does wafer level reliability assessment and testing methodology integrate into the semiconductor manufacturer's overall reliability assurance and improvement strategy? What wafer level tests are appropriate and when should they be utilized? Wafer level reliability has made the evolutionary step from academia to manufacturing actuality. This paper provides a conceptual focus for where and when wafer level reliability is utilized in a state-of-the-art semiconductor manufacturing environment. Special emphasis is placed on the use of wafer level reliability testing for introducing and qualifying new semiconductor technology, as well as controlling production once the technology has been qualified.

As semiconductor technology continues its drive toward smaller geometries and faster speeds, the demands placed on a metal system continue to increase. While conservative design rules may theoretically keep the metal reliability identical over a wide range of geometries, the margin of error becomes increasingly smaller. This increased sensitivity has driven the development of an improved set of test structures designed to increase the amount of information obtained from a metal process evaluation. Data are presented to show inadequacies of the current test methods for assessing metal reliability. A proposal is made for an improved set of metal test structures and test techniques aimed at more accurately evaluating the thermal and current density effects on electromigration, estimating the physical `random defect density' in the metal and for estimating the process variation across a large sample of die, wafers and lots.

Due to their favorable structural and electrical properties, air bridges are used extensively by silicon and GaAs monolithic microwave integrated circuit (MMIC) designers. Fabrication of such structures using the conventional techniques is complex. In this paper novel construction of air bridge structures of up to 7.5 micrometers high using an ultra violet (UV) stabilized bi-layer photoresist process, evaporated metal scheme, and lift-off patterning procedure, is realized. Deep UV stabilization of positive photo resist is discussed. Removal of the hardened resist via organic photo resist stripper is addressed.

Wafer-level monitoring of electromigration is widely investigated. For this purpose, test structures with specific geometrical features have been proposed allowing very accelerated tests; they are called `SWEAT' structures. The aim of this contribution is to present a method for the study of the thermal behavior of such devices. Laser probing offers a contactless investigation method with excellent lateral resolution, compared with the classical IR thermography. This method allows us to determine the temperature profile along the SWEAT structure axis. Electromigration data (i.e., failure location) are presented and interpreted based on the knowledge of the temperature along the structure.

Electron cyclotron resonance plasma-enhanced chemical vapor deposition has been used to deposit silicon oxide for use as an inter-layer dielectric between high aspect ratio metal lines. The energy from a 2.45 GHz microwave field in the presence of a divergent magnetic field is absorbed by O₂ and Ar gas to create a high density, low energy plasma. The silicon source gas, SiH₄, reacts with excited O species to initiate oxide deposition, during which the film is simultaneously etched by Ar and O ions. The gap fill capability and the degree of etching depend primarily on the radio frequency power applied to the wafer chuck. Films deposited using O₂/SiH₄ gas flow ratios ranging from 0.9 to 2.5 were measured using ellipsometry, FTIR, RBS, NRA, and MOS capacitors. The stoichiometry, refractive index, and dielectric constant are primarily controlled by the O₂/SiH₄ ratio. Films with a low relative dielectric constant can be deposited at rates in excess of 5000 angstroms/min with an etch component high enough to provide gap fill of high aspect ratio structures, thus making ECR CVD a viable tool for the current and future needs of the microelectronics industry.

As the VLSI/ULSI device density is increasing common failure mechanisms, such as internal latch-up phenomenon in sea-of-gate ASIC devices, are surfacing and becoming an important reliability issue. The traditional latch-up phenomenon sensitivity assessment techniques are no longer adequate; because the phenomenon is not limited to causes externally induced at the device peripherals but in process-induced defects as well. Therefore, an understanding of this effect is critical to both manufacturing and engineering communities. The purpose of this paper is to report a study of latch-ups in sea-of-gate (continuous arrays) ASIC devices. Two techniques, traditional and laser-induced testings, are presented.

Advanced sputtering equipment performance is affected by numerous system parameters. In this work, the effect of target crystallographic orientation, grain size, atomic channeling, and gas scattering have been incorporated into Monte Carlo computer simulations of advanced planar sputtering systems. A grid of polygons was created over the target area by the computer program. Each polygon of the grid represented an individual grain with a discrete crystal orientation. Crystallographic orientation distribution function (ODF) files were obtained for a number of polycrystalline targets through pole figure x ray analysis and harmonic texture analysis. The ODF files were used to assign discrete crystal orientations to each polygon. The program simulated the sputtering process by choosing a location on the target, based on the depth profile of a sputtered target and finally calculating the sputtered atom emission angles from the crystal orientation of that grain.