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Triple-level metal process for high-performance and high-density 0.6-μm/5-V application-specific integrated circuits
Spin on glass (SOG)-based planarization scheme compatible with a stacked via multilevel metal process
Spin on glass (SOG) etch-back planarization process: an industrial solution for 0.5-μm CMOS TLM technology
Application of APCVD TEOS/ozone thin films in < 0.5-μm IC fabrication: trench and intermetal dielectric isolation and gap fill
Temperature measurements on metallic lines under current stresses by laser probing and correlation with electromigration tests at wafer level
Properties of silicon oxide deposited by electron-cyclotron-resonance plasma-enhanced chemical vapor deposition