For time-critical industrial machine vision applications, a dedicated imager has been developed. The camera can be programmed to operate in several resolutions, by binning the signal charges of neighboring pixels on the sensor plane itself. Additionally the readout window was made programmable and an electronic shutter function was implemented. This square 256 X 256 imager was fabricated in a standard 1.5 micrometers CMOS technology. The readout occurs in two phases. After transferring in parallel a row of charges to 256 charge sensitive amplifiers, these signals are coupled to a single output amplifier. By controlling the sequence of addresses and reset pulses of the amplifiers, charges of different pixels are accumulated. This way multiple resolutions can be programmed. The imager is operated at data rates up to 10 MHz providing about 125 full images per second. At lower resolution, even higher frame rates are obtained. The signal to noise ratio is about 35 dB. This paper reports on the fixed pattern noise, response, speed and smear behavior of this imager.
A novel arrangement of gates on front-side-illuminated CCDs can leave up to 50% of the active detector area open to the epitaxial layer, allowing for enhanced response in the near UV spectral region. Important physical and operating properties and parameters (quantum efficiency and charge transfer efficiency) of two variations of the basic device are described.
Recent research results regarding the investigation of CMOS active pixel image sensors (APS) are reported. An investigation of various designs for the pixel, including photogate devices of various geometries and photodiode devices, has been performed. Optoelectronic performance including intrapixel photoresponse maps taken using a focused laser scanning apparatus are presented. Several imaging arrays have also been investigated. A 128 X 128 image sensor has been fabricated and characterized. Both p-well and n-well implementations have been explored. The demonstrated arrays use 2 micrometers CMOS design rules and have a 40 X 40 micrometers pixel pitch. Typical design fill-factor is 26%. Output sensitivity is 3.7 (mu) V/e- for the p-well devices and 6.5 (mu) V/e- for the n-well devices. Read noise is less than 40 e- rms for the baseline designs. Dynamic range has been measured to be over 71 dB using a 5 V supply voltage. The arrays are random access with TTL control signals. Results regarding on-chip suppression of fixed pattern noise also are presented.
A novel image sensor with image smoothing capability is described. The image smoothing is performed in real time by a neuron MOSFET implemented on-chip. The neuron MOSFET has multiple input gates and a floating gate. The floating gate is capacitively coupled to the input gates, thereby performing gate-level weighted-sum operations. A pixel output node of the image sensor is connected to the input gates of several neuron MOSFETs which are implemented on the periphery of the imaging area. The pixel output is weighted by the input gate's capacitance value and summed up on the floating gate. Thus the filter characteristic is determined by the input gates' capacitance values and the number of pixels connected to the input gates of a neuron MOSFET. An active pixel sensor approach is suitable for the architecture because of its large driving capability. SPICE simulation results and experimental results of a linear array and a test structure are reported. The linear array outputs smoothed image and raw pixel signal. An edge detected signal can be obtained by subtracting the smoothed signal from the pixel signal. An area array configuration is also introduced.
An assessment of solid-state UV/visible image sensor technology for future NASA missions is presented. The paper attempts to summarize the state of the art in image sensor technology in the United States, Canada, Japan, and Europe. The state of the art and future trends are compared to a forecast of future NASA needs in scientific image sensors for planetary exploration, earth science, astrophysics, and spacecraft systems such as star trackers and optical communications.
We describe an interline CCD imaging array which features high-speed, on-chip, parallel A/D conversion. In addition, we present test results from fabricated devices. The imaging chip was fabricated through MOSIS in a double-poly 2.0 micrometers CCD/CMOS technology on a chip with total area 2.25 mm X 2.22 mm. The chip is composed of a 28 X 39 pixel, interline imaging array, and a bank of 39 single-slope CCD/CMOS A/D converters; the converters function in parallel to achieve effective high-speed A/D conversion. Chip output is a stream of 8-bit digital data in which each 8-bit value corresponds to the light level at a pixel. Once an image has been captured, a set of parallel CCD shift registers transfer the data one column at a time to the parallel A/D converters. The analog data from each column is then converted in parallel and the resulting digital values are read out serially.
In earlier work, a model of the back illuminated CCD was presented and used to predict optical quantum efficiency. In this work we expand on the model and find an analytical solution for the probability of collection of a carrier generated at a given depth. We apply our solution to find the theoretical quantum efficiencies for both electron bombardment and optical illumination and compare them to measurements taken on thinned, backside-enhanced, non- AR coated devices. A single set of parameters is found which shows a reasonable fit to both sets of data. Earlier models of electron-bombarded CCDs have failed to explain the measured nonzero gain at low energies, however our model shows nonzero gain at all energies.
A second generation of high-frame-rate 512 X 512 and 1024 X 1024 pixel CCD imagers has been fabricated. These thinned, back-illuminated frame transfer imagers, designed for optical signal-processing applications, employ a split-frame transfer into dual storage registers and multiple output ports for increased frame rates. Reported here are measured characteristics of 16-port 512 X 512 and 32-port 1024 X 1024 imagers from the second design/fabrication cycle. Data are presented characterizing quantum efficiency, dynamic range, antiblooming control operation, high-speed performance, and on-chip correlated-double-sampling amplifier noise.
Two multiport, second-generation CCD imager designs have been fabricated and successfully tested. They are a 16-port 512 X 512 array and a 32-port 1024 X 1024 array. Both designs are back illuminated, have on-chip CDS, lateral blooming control, and use a split vertical frame transfer architecture with full frame storage. The 512 X 512 device has been operated at rates over 800 frames per second. The 1024 X 1024 device has been operated at rates over 300 frames per second. The major changes incorporated in the second-generation design are, reduction in gate length in the output area to give improved high-clock-rate performance, modified on-chip CDS circuitry for reduced noise, and optimized implants to improve performance of blooming control at lower clock amplitude. This paper discusses the imager design improvements and presents measured performance results at high and moderate frame rates. The design and performance of three moderate frame rate cameras are discussed.
Philips Imaging Technology has succeeded in fabricating an image sensor especially suited for digital image processing. The FT12 sensor is of the frame transfer type and designed for 2/3' optical format. It has a high resolution (1024 X 1024 in interlaced mode), overexposure handling by means of vertical anti-blooming and square pixels of 7.5 micrometers by 7.5 micrometers . The data rate is 60 fields per second in interlaced mode. Its single output register can run up to 40 MHz. The register can be clocked bi-directionally, which makes it possible to produce a mirrored image. These properties make it perfectly suited for machine vision applications, like pattern recognition and real-time process monitoring. The paper describes the sensor, simulation results, measurements, as well as the implementation of the sensor in a camera module.
We describe the architecture of high-frame-rate, frame-interline-transfer CCD arrays designed for optical signal processing applications. A gain-compression scheme is implemented in the pixel structure to increase the optical detection dynamic range. Simulation results are presented and compared with test results of imagers from the first fabrication lot.
We present a document imaging system using page-sized amorphous silicon 2D sensor arrays. Two arrays of approximately 8' X 10' in area are used. One has 512 X 560 pixels and the other one has 1536 X 1920 pixels. The scanner can operate in either a contact imaging mode or a projection mode. The system has a signal-to-noise ratio of 1000, limited by the noise in the readout amplifier. Using sequential flash lamp exposures with appropriate color filters, one can achieve color imaging of a document with a perfect registration. In this paper, we describe sensor structure, electrical properties, and system design of the imager. We discuss the potential of the amorphous silicon sensor array as an electronic color document input device. The high sensitivity of the array allows high-speed scanning of a document and medical x-ray imaging (with a phosphor layer).
We have developed a contact-type color image sensor for use in color scanners and color copy machines. This sensor features a high-precision array of phototransistor chips fitted with RGB color filters. It scans an A4-size document in 10 seconds with a high resolution 400 DPI. This sensor is compact and easy to use, and does not require special sensor drivers, a read-position compensation memory or spurious color suppression circuit. A color image sensor, rod lens array, fluorescent lamp, and drive circuit board are built in.
A thinned-CCD mosaic was fabricated from four Loral 2048 X 2048 edge-buttable CCDs. Thinning was performed on the whole wafer with subsequent dicing and handling facilitated by bonding the thinned wafer to a glass plate. Packaging of the devices involved a `flip-chip' wire-bonding technique followed by chemical dissolution of the glass support. The fabrication process was designed to minimize the gaps between devices and retain a high degree of flatness in the finished CCDs.
A Charge Injection Device Technologies 512 X 512 CID array has been tested at liquid nitrogen temperature to assess its suitability for use in low light applications. The CID-38 chip used was installed in a SICam dewar/electronics from CIDTEC. For this particular system the noise floor was measured to be approximately equals 260 electrons rms for a single readout. Using the nondestructive readout option an approximately equals (root)N, where N is the number of readouts, improvement in this noise figure can be achieved. The average dark current at 77 degree(s)K was not measurable in a three-hour dark integration.
A new European-format CID imager with improved radiation tolerance was developed to meet the operational requirements of the burgeoning international nuclear power generation and waste management markets. Incorporating an inherently radiation tolerant CID architecture fabricated using a new improved radiation resistant process, the imager is designed to survive total dose radiation of more than 106 rads (gamma-Sl) in environments greater than 105 rads/hr (gamma-Sl). The imager format is 786 pixels/row by 612 rows mapped into an 11 MM diagonal optical format. The device incorporates an 11.5 micron2 pixel structure that can be read out either in an interlaced CCIR TV compatible or progressive 25 Hz mode. Additionally, the imager incorporates a deep depletion high resistivity structure that makes it suitable for sensing x ray, nuclear as well as E-beam forms of radiation. The CID device design and tooling was completed during 1993. Sample devices were fabricated and tested during late 1993 and early 1994. Preliminary test results together with further imager and camera development plans are included herein.
A 4096 X 2048-pixel three-side buttable scientific CCD imager was designed and fabricated for use in electronic imaging applications that require mosaics of many closely spaced large area CCDs that have good low-light-level performance. The three-side buttable CCD design, which allows 8192 X (N X 2048) pixel mosaicking, was fabricated using a custom three-level polyscientific CCD process. The CCD has 15 micron square pixels and employs a full-frame MPP mode device architecture with a single split serial shift register and two on-chip amplifiers. Excellent performance characteristics were demonstrated, including less than 5 electron noise at a 50 kHz output data rate, charge transfer efficiency greater than 0.999997, and an exceptionally low density of small signal charge traps at the characterization temperature. The on-chip CCD amplifier high-frequency operation was characterized separately and the amplifier was found to support a 5-MHz output data rate corresponding to a readout cycle of 0.84 seconds for higher frame rate applications.
Results are presented on the fabrication and characterization of a 4 K X 2 K three-side buttable CCD produced by Orbit Semiconductor. This first run of wafers was produced to test the ability of Orbit to produce high-quality scientific CCDs with the characteristics required for detectors to be used in optical instruments of the Keck Observatory. Also on the wafer are two 2 K X 2 K devices. Similar devices have been fabricated for us previously by Loral/Fairchild. Extensive characterization of the Loral devices has taken place over the past few years, so interest is high about the possibility that Orbit might become a second source for similar detectors. This paper presents the first results on the 4 K X 2 K CCDs, including measurements of charge transfer efficiency, low-temperature dark current, on-chip amplifier readout noise, localized charge traps, full well, and responsive quantum efficiency.
The applicability of large-area full-frame CCD image sensor technology to large optical format aerial reconnaissance applications has been recently demonstrated. The requirements of low-contrast, high-resolution imaging at high frame rates have generated the need for a manufacturable, multitap, small-pitch, wafer-scale CCD image sensor technology. The added requirement of incorporation of electronic motion compensation at the focal plane has generated the need for multisegmented full-frame area array architectures. Characterization results from the newly developed 5040 X 5040 element, eight-tap, full-frame image sensor with multisegmentation for electronic motion compensation are discussed. Experimental determination of resistive-capacitive time constants for metal strapped vertical clock busses on wafer-scale sensors is discussed.
A high-performance time delay and integration (TDI) CCD image sensor has been developed at DALSA for color scanning applications. The imager comprises three individual 2048 X 32 linear arrays, each with its own color filter for spectral separation. The number of stages in each TDI array can be selected separately in blocks of 4, 8, 16, and 32 for optimum sensitivity over a wide range of illumination conditions. The device is fabricated using a dual metal NMOS buried channel CCD process with a 3-phase, 3-poly imaging region for increased charge storage. The pixel height and pitch is 14 micrometers and the center to center separation between the color channels is 560 micrometers . The data is read out using a 2-phase CCD shift register with a 14 micrometers pitch at an output data rate of 15 MHz per output. The die size is 31.4 mm X 4.3 mm and is housed in a 40 pin, 2.0' X 0.61', dual in line package. In this paper the authors discuss the design and the performance evaluation of the device.
CCD devices fabricated on low-resistivity silicon epi (30 - 60 (Omega) -cm) exhibit satisfactory imaging characteristics in the visible spectrum but inferior imaging characteristics in the near infrared and x ray regions. This is a result of the greater penetration depth of the photons, which tend to travel beyond the depletion regions under the CCD gates causing optical crosstalk and poor responsivity. This represents a performance limiting issue for acousto-optical applications and scientific imaging. CCD devices fabricated on high-resistivity silicon epi (>= 1000 (Omega) -cm) with increased epi layer thickness will exhibit superior imaging performance for near-infrared and x-ray photons. This is because the width of the depletion regions is much greater compared to devices on conventional substrates. DALSA has fabricated CCD structures on high-resistivity substrates and has examined their performance, in particular imaging behavior in the near-infrared region of the spectrum. We also examine the behavior of the nonimaging circuitry associated with the CCD such as the output amplifiers.