PROCEEDINGS VOLUME 2875
MICROELECTRONIC MANUFACTURING 1996 | 16-18 OCTOBER 1996
Microelectronic Device and Multilevel Interconnection Technology II
MICROELECTRONIC MANUFACTURING 1996
16-18 October 1996
Austin, TX, United States
SOI CMOS and Trench Isolation
Proc. SPIE 2875, Stability and reliability of fully depleted SOI MOSFETs, 0000 (13 September 1996); doi: 10.1117/12.250855
Proc. SPIE 2875, High-performance metal-gate SOI CMOS fabricated by ultraclean low-temperature process technologies, 0000 (13 September 1996); doi: 10.1117/12.250865
Proc. SPIE 2875, Study of integration issues in shallow trench isolation for deep submicron CMOS technologies, 0000 (13 September 1996); doi: 10.1117/12.250874
Proc. SPIE 2875, Trench isolation technology for high-performance complementary bipolar devices, 0000 (13 September 1996); doi: 10.1117/12.250883
Hot Carrier and Temperature Effects
Proc. SPIE 2875, Key issues in evaluating hot-carrier reliability, 0000 (13 September 1996); doi: 10.1117/12.250889
Proc. SPIE 2875, Effect of the pLDD implantation dose on pMOS transistor characteristics, 0000 (13 September 1996); doi: 10.1117/12.250890
Proc. SPIE 2875, Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C, 0000 (13 September 1996); doi: 10.1117/12.250891
Proc. SPIE 2875, Digital standard cells and operational amplifiers for operation up to 250 degrees C using low-cost CMOS technology, 0000 (13 September 1996); doi: 10.1117/12.250892
CMOS Reliability and Technology
Proc. SPIE 2875, Reliability scaling in deep submicron MOSFETs, 0000 (13 September 1996); doi: 10.1117/12.250856
Proc. SPIE 2875, Optimizing a manufacturing submicron CMOS process for low-voltage applications, 0000 (13 September 1996); doi: 10.1117/12.250857
Proc. SPIE 2875, Device and process integration for a 0.55-um channel length CMOS device, 0000 (13 September 1996); doi: 10.1117/12.250858
Proc. SPIE 2875, Manufacturing sensitivity analysis of a 0.18-micron NMOSFET, 0000 (13 September 1996); doi: 10.1117/12.250859
CMOS Technology
Proc. SPIE 2875, High-performance 0.25-um CMOS technology for fast SRAMs, 0000 (13 September 1996); doi: 10.1117/12.250860
Proc. SPIE 2875, Lg=0.25-um CMOS devices with N+-polycide gate for 3.3-V application, 0000 (13 September 1996); doi: 10.1117/12.250861
Proc. SPIE 2875, Shadowing of lightly doped drain implants due to gate etch profiles and implanter configurations, 0000 (13 September 1996); doi: 10.1117/12.250862
Proc. SPIE 2875, Use of elevated source/drain structure in sub-0.1 um NMOSFETs, 0000 (13 September 1996); doi: 10.1117/12.250863
Thin Dielectrics and Emerging Technologies
Proc. SPIE 2875, Materials and processing issues in the development of N2O/NO-based ultrathin oxynitride gate dielectrics for CMOS ULSI applications, 0000 (13 September 1996); doi: 10.1117/12.250864
Proc. SPIE 2875, Scaling considerations of interpoly oxide-nitride-oxide dielectric for high-density DRAM applications, 0000 (13 September 1996); doi: 10.1117/12.250866
Proc. SPIE 2875, Influence of carbon contamination on ultrathin gate oxide reliability, 0000 (13 September 1996); doi: 10.1117/12.250867
Proc. SPIE 2875, Computer-aided optimization of ion-implanted charge bump parameters for rf silicon SDR, 0000 (13 September 1996); doi: 10.1117/12.250868
Memory Technologies
Proc. SPIE 2875, Gate oxide field design in the sub-10-nm region, 0000 (13 September 1996); doi: 10.1117/12.250869
Proc. SPIE 2875, Scalability of conventional and sidewall-sealed LOCOS technology for 256-Mbit DRAM array and periphery isolation, 0000 (13 September 1996); doi: 10.1117/12.250870
Proc. SPIE 2875, Pass transistor and isolation design methodology and its implementation for improved manufacturability for 256-Mbit DRAM and beyond, 0000 (13 September 1996); doi: 10.1117/12.250871
Intermetal Dielectric and Planarization
Proc. SPIE 2875, Reflow of Al-Cu by low-temperature germane reactions, 0000 (13 September 1996); doi: 10.1117/12.250872
Proc. SPIE 2875, Characterization of W CMP processes for 200-mm applications, 0000 (13 September 1996); doi: 10.1117/12.250873
Proc. SPIE 2875, Integration of ICP high-density plasma CVD with CMP and its effects on planarity for sub-0.5-um CMOS technology, 0000 (13 September 1996); doi: 10.1117/12.250875
Proc. SPIE 2875, Comparison of spin-on materials in IMD planarization, 0000 (13 September 1996); doi: 10.1117/12.250876
Proc. SPIE 2875, SOG etch-back process induced surface roughness, 0000 (13 September 1996); doi: 10.1117/12.250877
Advanced Metallization and Metal Etching
Proc. SPIE 2875, Process integration of TDEAT-based MOCVD TiN as diffusion barrier for advanced metallization, 0000 (13 September 1996); doi: 10.1117/12.250878
Proc. SPIE 2875, Submicron metal etch integration study, 0000 (13 September 1996); doi: 10.1117/12.250879
Proc. SPIE 2875, Effects of process parameters on microloading in subhalf-micron aluminum etching, 0000 (13 September 1996); doi: 10.1117/12.250880
Proc. SPIE 2875, Comparison of the Ti/TiN/AlCu/TiN stack with TiN/AlCu/Ti/TiN stack for application in ULSI metallization, 0000 (13 September 1996); doi: 10.1117/12.250881
Proc. SPIE 2875, Intermetallic compound formation in hot aluminum metallization and its effect on etching and electromigration, 0000 (13 September 1996); doi: 10.1117/12.250882
Novel Interconnection Technologies
Proc. SPIE 2875, Copper metallization for on-chip interconnects, 0000 (13 September 1996); doi: 10.1117/12.250884
Proc. SPIE 2875, Interconnection schemes for parasitics optimization, 0000 (13 September 1996); doi: 10.1117/12.250885
Proc. SPIE 2875, Tungsten plug contact and via integration for subhalf-micron technology, 0000 (13 September 1996); doi: 10.1117/12.250886
Proc. SPIE 2875, Structured CVD-silicon carbonitride coatings, 0000 (13 September 1996); doi: 10.1117/12.250887
Plenary Paper
Proc. SPIE 2875, Productivity improvement through industrial engineering in the semiconductor industry, 0000 (13 September 1996); doi: 10.1117/12.250888
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