MICROELECTRONIC MANUFACTURING
1-2 October 1997
Austin, TX, United States
Fluctuations and Device Design
Proc. SPIE 3212, Statistical analysis of dynamic-random-access-memory data-retention characteristics, 0000 (27 August 1997); doi: 10.1117/12.284578
Proc. SPIE 3212, Characterization of Vth fluctuation in 0.15-um n-MOSFETs for gigabit DRAM cell transistors, 0000 (27 August 1997); doi: 10.1117/12.284589
Proc. SPIE 3212, Methods for the design of microelectronic devices and process flows for manufacturability, 0000 (27 August 1997); doi: 10.1117/12.284600
Proc. SPIE 3212, Methodology for optimizing transistor performance, 0000 (27 August 1997); doi: 10.1117/12.284610
Proc. SPIE 3212, Device performance and optimization for 5th- and 6th-generation microprocessors, 0000 (27 August 1997); doi: 10.1117/12.284617
Dielectrics/Surface Preparation
Proc. SPIE 3212, Surface preparation, growth, and characterization of ultrathin gate oxides for scaled CMOS applications, 0000 (27 August 1997); doi: 10.1117/12.284618
Proc. SPIE 3212, Optimization of pre-gate clean technology for a 0.35-um dual-oxide/dual-voltage CMOS process, 0000 (27 August 1997); doi: 10.1117/12.284619
Proc. SPIE 3212, Ultrathin oxide for sub-0.25-um technology in silicon ICs: impact of stacking and nitridation, 0000 (27 August 1997); doi: 10.1117/12.284620
Proc. SPIE 3212, Process optimization of dual-gate CMOS, 0000 (27 August 1997); doi: 10.1117/12.284621
Proc. SPIE 3212, Quasi-breakdowns in ultrathin dielectrics, 0000 (27 August 1997); doi: 10.1117/12.284579
Advanced Technologies and RF Applications
Proc. SPIE 3212, Potential of rf Si-MOS LSI technology, 0000 (27 August 1997); doi: 10.1117/12.284580
Proc. SPIE 3212, Thin-film integration for nanoscale and high-frequency electronics on Si, 0000 (27 August 1997); doi: 10.1117/12.284581
Proc. SPIE 3212, Si selective epitaxial growth technology using UHV-CVD and its application to LSI fabrication, 0000 (27 August 1997); doi: 10.1117/12.284582
Proc. SPIE 3212, Applications of silicon-germanium-carbon in MOS and bipolar transistors, 0000 (27 August 1997); doi: 10.1117/12.284583
Proc. SPIE 3212, Strained Si NMOSFET on relaxed Si1-xGex formed by ion implantation of Ge, 0000 (27 August 1997); doi: 10.1117/12.284584
Contact and Source/Drain Junction Design
Proc. SPIE 3212, Shallow source/drain extension formation using antimony and indium pre-amorphization schemes for 0.18- to 0.13-um CMOS technologies, 0000 (27 August 1997); doi: 10.1117/12.284585
Proc. SPIE 3212, Low-energy BF2, BCl2, and BBr2 implants for ultrashallow P+-N junctions, 0000 (27 August 1997); doi: 10.1117/12.284586
Proc. SPIE 3212, Impact of nitrogen ion-implantation on deep submicron SALICIDE process, 0000 (27 August 1997); doi: 10.1117/12.284587
Proc. SPIE 3212, Sheet resistance requirements for the source/drain regions of 0.11-um gate length CMOS technology, 0000 (27 August 1997); doi: 10.1117/12.284588
Proc. SPIE 3212, Scaling self-aligned contacts for 0.25-um and below, 0000 (27 August 1997); doi: 10.1117/12.284590
Low-Voltage and Scaled MOSFETs
Proc. SPIE 3212, Advantages of SOI technology in low-voltage ULSIs, 0000 (27 August 1997); doi: 10.1117/12.284591
Proc. SPIE 3212, Low-threshold 0.6-um MOSFET for low-voltage rf applications, 0000 (27 August 1997); doi: 10.1117/12.284592
Proc. SPIE 3212, Design of 0.18-micron NMOSFETs for low-power applications, 0000 (27 August 1997); doi: 10.1117/12.284593
Proc. SPIE 3212, Prediction of CMOS transistor performance at 0.10-um gate length using tuned simulations, 0000 (27 August 1997); doi: 10.1117/12.284594
Proc. SPIE 3212, 0.18-um gate length CMOS devices with N+ polycide gate for 2.5-V application, 0000 (27 August 1997); doi: 10.1117/12.284595
Process Dependence on Device Variation and Reliability
Proc. SPIE 3212, Impact of photoresist taper and implant tilt angle on the interwell isolation of subquarter-micron CMOS technologies, 0000 (27 August 1997); doi: 10.1117/12.284596
Proc. SPIE 3212, Wafer-scale modeling of pattern effect in oxide chemical mechanical polishing, 0000 (27 August 1997); doi: 10.1117/12.284597
Proc. SPIE 3212, Improvement of edge leakage in PBL-isolated SOI NMOSFETs, 0000 (27 August 1997); doi: 10.1117/12.284598
Proc. SPIE 3212, Hot-carrier degradation for deep-submicron N-MOSFETs introduced by back-end processing, 0000 (27 August 1997); doi: 10.1117/12.284599
Proc. SPIE 3212, Effect of local interconnect etch-stop layer on channel hot-electron degradation, 0000 (27 August 1997); doi: 10.1117/12.284601
Proc. SPIE 3212, Plasma-induced charging damage in P+-polysilicon PMOSFETs, 0000 (27 August 1997); doi: 10.1117/12.284602
Proc. SPIE 3212, Applicability of RTCVD and LPCVD nitride spacers for sub-0.18-um CMOS technologies, 0000 (27 August 1997); doi: 10.1117/12.284603
Inverse Short Channel Effect and Implant Damage Modeling
Proc. SPIE 3212, Boron segregation in As-implanted Si due to electric field and transient enhanced diffusion, 0000 (27 August 1997); doi: 10.1117/12.284604
Proc. SPIE 3212, Nitrogen implantation: reverse short channel effects improvement and its drawbacks, 0000 (27 August 1997); doi: 10.1117/12.284605
Proc. SPIE 3212, Tuned MEDICI simulator including inverse short channel effect for sub-0.18-um CMOS technologies, 0000 (27 August 1997); doi: 10.1117/12.284606
Proc. SPIE 3212, Computationally efficient ion implantation damage model: modified Kinchin-Pease model, 0000 (27 August 1997); doi: 10.1117/12.284607
Poster Session
Proc. SPIE 3212, SiGe/Si vertical PMOSFET device design and fabrication, 0000 (27 August 1997); doi: 10.1117/12.284608
Proc. SPIE 3212, Low-energy model for ion implantation of arsenic and boron into (100) single-crystal silicon, 0000 (27 August 1997); doi: 10.1117/12.284609
Proc. SPIE 3212, Si1-x-yGexCy channel heterojunction PMOSFETs, 0000 (27 August 1997); doi: 10.1117/12.284611
Proc. SPIE 3212, Characteristics of BaxSr1-xTiO3 thin films by metallorganic chemical vapor deposition for ultrahigh-density DRAM application, 0000 (27 August 1997); doi: 10.1117/12.284612
Proc. SPIE 3212, Constant current-stress-induced breakdown of reoxidized nitrided oxide (ONO) in flash memory devices, 0000 (27 August 1997); doi: 10.1117/12.284613
Proc. SPIE 3212, Characterization of polymer formation during SiO2 etching with different fluorocarbon gases (CHF3, CF4, C4F8), 0000 (27 August 1997); doi: 10.1117/12.284614
Proc. SPIE 3212, Narrow-channel transistor threshold self-adjustment technique for ULSI with LOCOS isolation, 0000 (27 August 1997); doi: 10.1117/12.284615
Proc. SPIE 3212, Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications, 0000 (27 August 1997); doi: 10.1117/12.284616
Back to Top