PROCEEDINGS VOLUME 3506
MICROELECTRONIC MANUFACTURING | 20-24 SEPTEMBER 1998
Microelectronic Device Technology II
MICROELECTRONIC MANUFACTURING
20-24 September 1998
Santa Clara, CA, United States
Dielectrics/Gate Technology
Proc. SPIE 3506, Remote plasma nitrided oxides for ultrathin gate dielectric applications, 0000 (4 September 1998); doi: 10.1117/12.323956
Proc. SPIE 3506, Advanced gate technology for sub-0.25-um CMOSFETs, 0000 (4 September 1998); doi: 10.1117/12.323966
Proc. SPIE 3506, Feasibility study to determine the suitability of using TiN/W and Si1-xGex as alternative gate materials for sub-0.1-um gate-length PMOS devices, 0000 (4 September 1998); doi: 10.1117/12.323981
Proc. SPIE 3506, High-k scaling for gate insulators: an insightful study, 0000 (4 September 1998); doi: 10.1117/12.323991
Source/Drain Junctions and Salicide
Proc. SPIE 3506, Laser thermal processing for shallow junction and silicide formation, 0000 (4 September 1998); doi: 10.1117/12.323992
Proc. SPIE 3506, Shallow p-type source/drain extension formation using B2H6 plasma doping for deep submicron CMOS, 0000 (4 September 1998); doi: 10.1117/12.323993
Proc. SPIE 3506, Process window characterization of RTA source/drain anneal, 0000 (4 September 1998); doi: 10.1117/12.323994
Proc. SPIE 3506, Source/drain formation using cobalt silicide as diffusion source for deep submicron nMOS, 0000 (4 September 1998); doi: 10.1117/12.323995
Proc. SPIE 3506, Self-aligned silicide process technology for sub-0.25-um geometries, 0000 (4 September 1998); doi: 10.1117/12.323957
Proc. SPIE 3506, Evaluation of Mo-doped Ti salicide process for sub-0.18-um CMOS, 0000 (4 September 1998); doi: 10.1117/12.323958
Integration and Manufacturability
Proc. SPIE 3506, Sub-half-micron device fabricated with 2-um generation facilities, 0000 (4 September 1998); doi: 10.1117/12.323959
Proc. SPIE 3506, Manufacturing multilevel metal CMOS with deuterium anneals for improved hot-carrier reliablility, 0000 (4 September 1998); doi: 10.1117/12.323960
Proc. SPIE 3506, Improving manufacturability of an rf graded channel CMOS process for wireless applications, 0000 (4 September 1998); doi: 10.1117/12.323961
Proc. SPIE 3506, Optimized shallow trench isolation for sub-0.18-um ASIC technologies, 0000 (4 September 1998); doi: 10.1117/12.323962
Proc. SPIE 3506, Performance, standby power, and manufacturability trade-off in transistor design consideration for 0.25-um technology, 0000 (4 September 1998); doi: 10.1117/12.323963
Process Design for Scaled CMOS
Proc. SPIE 3506, Yield management by threshold voltage adjustment in back-end process, 0000 (4 September 1998); doi: 10.1117/12.323965
Proc. SPIE 3506, Material study of indium implant under channel doping conditions, 0000 (4 September 1998); doi: 10.1117/12.323967
Proc. SPIE 3506, New process for manufacturing thin SiGe and SiGeC epitaxial films on silicon by ion implantation and excimer laser annealing, 0000 (4 September 1998); doi: 10.1117/12.323972
Proc. SPIE 3506, Impact of silicon-type floating gate on EEPROM performance, 0000 (4 September 1998); doi: 10.1117/12.323973
SOI and Sub-100-nm CMOS Technologies
Proc. SPIE 3506, Ultrathin film fully depleted CMOS/SIMOX technology with selective CVD tungsten and its application to LSIs, 0000 (4 September 1998); doi: 10.1117/12.323974
Proc. SPIE 3506, Sub-50-nm PtSi Schottky source/drain MOSFETs, 0000 (4 September 1998); doi: 10.1117/12.323975
Proc. SPIE 3506, Prediction of deep submicron CMOS transistor performance and comparison with projected performance trends using tuned simulations, 0000 (4 September 1998); doi: 10.1117/12.323976
Proc. SPIE 3506, Sub-100-nm and deep sub-100-nm MOS transistor gate patterning, 0000 (4 September 1998); doi: 10.1117/12.323977
Proc. SPIE 3506, Response-surface-based optimization of 0.1-um PMOSFETs with ultrathin gate stack dielectrics, 0000 (4 September 1998); doi: 10.1117/12.323978
Proc. SPIE 3506, Hot-carrier effects in sub-100-nm gate-length N-MOSFETs with thermal and nitrided oxide thickness down to 1.3 nm, 0000 (4 September 1998); doi: 10.1117/12.323979
Device and Process Simulation
Proc. SPIE 3506, New methodology of simulating pocket-implanted sub-0.18-um CMOS, 0000 (4 September 1998); doi: 10.1117/12.323980
Proc. SPIE 3506, Optimum junction-depth design of the S/D extension regions (MDD) for sub-0.18-um CMOS technologies, 0000 (4 September 1998); doi: 10.1117/12.323982
Proc. SPIE 3506, Parasitic resistance analysis for deep submicron CMOS with inverse modeling, 0000 (4 September 1998); doi: 10.1117/12.323983
Proc. SPIE 3506, Experimental verification of a new physically based low-energy (<5 keV) ion implant model, 0000 (4 September 1998); doi: 10.1117/12.323984
Proc. SPIE 3506, Improved analytic models and efficient parameter extraction for computationally efficient 1D and 2D ion implantation modeling, 0000 (4 September 1998); doi: 10.1117/12.323985
Poster Session
Proc. SPIE 3506, Novel thin epi process for high-speed CB-CMOS, 0000 (4 September 1998); doi: 10.1117/12.323986
Proc. SPIE 3506, Production of ohmic contacts to AlxGa1-xAs of the n- and p-type conductivity with surface cleaning in atomic hydrogen, 0000 (4 September 1998); doi: 10.1117/12.323987
Proc. SPIE 3506, BJT avalanche breakdown voltage improvement by introduction of a floating p-layer in the epitaxial collector region, 0000 (4 September 1998); doi: 10.1117/12.323988
Proc. SPIE 3506, Optimum bandgap profile for a high-efficiency p-i-n a-Si: H solar cell, 0000 (4 September 1998); doi: 10.1117/12.323990
Plenary Papers
Proc. SPIE 3506, Microprocessor technology challenges through the next decade, 0000 (4 September 1998); doi: 10.1117/12.323968
Proc. SPIE 3506, Copper chip technology, 0000 (4 September 1998); doi: 10.1117/12.323969
Proc. SPIE 3506, Foundry technology trend, 0000 (4 September 1998); doi: 10.1117/12.323970
Proc. SPIE 3506, Equipment challenges for a total material system change: enabling device manufacturing at 130 nm and below, 0000 (4 September 1998); doi: 10.1117/12.323971
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